Demo Data from VLDB 2026 / reviewers in the wild / expert
Sayak Chakraborti
dblp:159/2776
· DBLP profile ↗
4ranked-venue papers
1as first author
3since 2021 · last 2024
0000-0001-8773-5808ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Parallel and multicore computing · 40% Cloud and datacenter computing · 24% Embedded and real-time systems · 24% |
Topics — the 5 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Cloud and datacenter computing › cluster resource management and scheduling
cluster resource management |
0.6 | 1 | 2022 | MAPPER: Managing Application Performance via Parallel Efficiency Regulation* · ACM Trans. Archit. Code Optim. 2022 |
Embedded and real-time systems › real-time scheduling
quality-of-service-aware scheduling |
0.6 | 1 | 2022 | MAPPER: Managing Application Performance via Parallel Efficiency Regulation* · ACM Trans. Archit. Code Optim. 2022 |
Parallel and multicore computing › parallel scheduling
runtime scheduling |
0.6 | 1 | 2022 | MAPPER: Managing Application Performance via Parallel Efficiency Regulation* · ACM Trans. Archit. Code Optim. 2022 |
Performance modeling and evaluation › performance monitoring
hardware performance counters |
0.2 | 1 | 2022 | MAPPER: Managing Application Performance via Parallel Efficiency Regulation* · ACM Trans. Archit. Code Optim. 2022 |
Processor architecture and microarchitecture
resource contention |
0.1 | 1 | 2019 | Managing application parallelism via parallel efficiency regulation: poster · PPoPP 2019 |
Methods — techniques the papers use, named apart from their topics
task-to-CPU placement · 0.6hardware performance counters · 0.6
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | Dynamic Idle Resource Leasing To Safely Oversubscribe Capacity At MetaabstractMeta maintains additional capacity within its infrastructure to ensure high availability for business workloads, accommodating user growth, temporal traffic variations, and unforeseen regional failures. However, this strategic choice inherently leads to underutilization of resources. We employ oversubscription as an effective strategy to mitigate infrastructure underutilization. Iyswarya Narayanan, Shivam Handa, Sayak Chakraborti, Pankit Thapar, Baohua Shan, Ariel Rao, Yuanlai Liu, Yuqing Wu, Qingyi Gao, Chris Chao-Chun Cheng, Sihan You, Louis Huang, Kenny Yu, Tengfei Mu, Parth Malani, Trey Lu, Peter Zhang |
SoCC | 4 |
| 2023 | Blast from the Past: Least Expected Use (LEU) Cache Replacement with Statistical HistoryabstractCache replacement policies typically use some form of statistics on past access behavior. As a common limitation, however, the extent of the history being recorded is limited to either just the data in cache or, more recently, a larger but still finite-length window of accesses, because the cost of keeping a long history can easily outweigh its benefit. Sayak Chakraborti, Zhizhou Zhang 0002, Noah Bertram, Chen Ding 0001, Sandhya Dwarkadas |
ISMM | 1 |
| 2022 | MAPPER: Managing Application Performance via Parallel Efficiency Regulation*abstractState-of-the-art systems, whether in servers or desktops, provide ample computational and storage resources to allow multiple simultaneously executing potentially parallel applications. However, performance tends to be unpredictable, being a function of algorithmic design, resource allocation choices, and hardware resource limitations. In this article, we introduce MAPPER, a manager of application performance via parallel efficiency regulation. MAPPER uses a privileged daemon to monitor (using hardware performance counters) and coordinate all participating applications by making two coupled decisions: the degree of parallelism to allow each application to improve system efficiency while guaranteeing quality of service (QoS), and which specific CPU cores to schedule applications on. The QoS metric may be chosen by the application and could be in terms of execution time, throughput, or tail latency, relative to the maximum performance achievable on the machine. We demonstrate that using a normalized parallel efficiency metric allows comparison across and cooperation among applications to guarantee their required QoS. While MAPPER may be used without application or runtime modification, use of a simple interface to communicate application-level knowledge improves MAPPER’s efficacy. Using a QoS guarantee of 85% of the IPC achieved with a fair share of resources on the machine, MAPPER achieves up to 3.3 \( \times \) speedup relative to unmodified Linux and runtime systems, with an average improvement of 17% in our test cases. At the same time, MAPPER violates QoS for only 2% of the applications (compared to 23% for Linux), while placing much tighter bounds on the worst case. MAPPER relieves hardware bottlenecks via task-to-CPU placement and allocates more CPU contexts to applications that exhibit higher parallel efficiency while guaranteeing QoS, resulting in both individual application performance predictability and overall system efficiency. Sharanyan Srikanthan, Sayak Chakraborti, Princeton Ferro, Sandhya Dwarkadas |
ACM Trans. Archit. Code Optim. | 2 |
| 2019 | Managing application parallelism via parallel efficiency regulation: posterabstractModern multiprocessor systems contain a wealth of compute, memory, and communication network resources, such that multiple applications can often successfully execute on and compete for these resources. Unfortunately, good performance for individual applications in addition to achieving overall system efficiency proves a difficult task, especially for applications with low parallel efficiency (speedup per utilized computational core). Limitations to parallel efficiency arise out of factors such as algorithm design, excess synchronization, limitations in hardware resources, and sub-optimal task placement on CPUs. Sharanyan Srikanthan, Princeton Ferro, Sayak Chakraborti, Sandhya Dwarkadas |
PPoPP | 3 |