To achieve high test coverage for scaled-down high-speed memory, the hardware complexity of the algorithmic pattern generator (ALPG) in automatic test equipment (ATE) has increased due to the demands of high-speed operation. However, the potential for further speed-up is constrained by the challenges associated with pipeline insertion and signal integrity preservation. Unlike ALPGs, test patterns in vector memory (VM) are generated by simply fetching pre-stored patterns without performing complex operations. Although its fetching logic is advantageous in high-speed operation, the speed of VM-based pattern generation is limited by the VM load speed. Furthermore, the limited VM capacity restricts the storage of extensive test patterns. To address the limitations of both approaches, a vector memory using bit-level address segmentation (VASE) that enables high-speed memory testing is proposed. VASE improves pattern generation speed by cyclically reusing test patterns while reducing the required VM capacity. Although VASE may impose some limitations on test algorithm coverage and incur overhead in logic area and power consumption, it still supports a wide range of commonly used test algorithms. Considering the speed improvements achieved, these trade-offs are acceptable for ATE applications.

Digital processing-in-memory (PIM) architectures have garnered significant attention for their ability to overcome the memory bottleneck in artificial intelligence (AI) acceleration. However, unlike conventional logic accelerators, dynamic random access memory (DRAM)-based digital PIMs tightly integrate compute and memory arrays within a single chip. This close coupling makes any logic fault directly affect stored data, leading to more critical system-level failures. Moreover, the coexistence of logic and memory components significantly increases testing complexity and fault localization difficulty. As AI is increasingly adopted in mission-critical domains such as autonomous driving, healthcare, and finance, the tolerance for computational errors continues to decline. In PIM-based AI accelerators, permanent faults originating from manufacturing processes can accumulate and propagate over repeated computations, making reliability and precision critical in safety-sensitive applications. To ensure high reliability, precise and independent fault diagnosis of all arithmetic units (AUs), including multipliers and adders, is essential. The proposed DPR-PIM architecture addresses this critical need by enabling complete per-unit diagnosis and fault localization. The DPR-PIM fully utilizes standard automatic test equipment (ATE) interfaces used in conventional memory testing, making it a practical and production-compatible solution. Moreover, DPR-PIM enables pipelined repair for single faults in adder stages based on accurate diagnosis results and applies fault blocking to prevent error propagation when multiple faults occur within the same adder stage or when faults occur in multipliers. By combining high test coverage, reliable repair mechanisms, and minimal area overhead, DPR-PIM offers a robust and scalable architecture for next-generation digital PIM systems.

Cultural heritage is essential for preserving the identity and history of civilizations, but its protection faces challenges from natural deterioration, environmental factors, and human activity. This study presents an intelligent monitoring system using an autonomous mobile robot, applied to Gongsanseong Fortress, a historic site in Korea. The system monitors structural damage at key points of interest, such as fortress walls and stone monuments, and also tracks long-term deterioration. It consists of an edge server for on-site data processing and localization, as well as a cloud server that performs deep learning-based damage detection. To assess potential collapse risks, a classification model is employed that considers factors including moisture and soil composition. Performance validation using data collected from Gongsanseong Fortress demonstrates the system’s effectiveness in damage detection, environmental impact assessment, and informed decision-making for heritage conservation.

With the rapid advancement of artificial intelligence (AI), there has been extensive research on AI accelerators to meet the demand for data-intensive analytics. Recently, low-power AI accelerators have been also developed to support battery-operated edge devices and minimize power consumption. However, traditional test architectures are insufficient for effectively testing such low-power AI accelerators. To address this issue, a robust test architecture for low-power AI accelerators has been proposed in this article. The proposed test architecture employs a simple clock-gating technique in systolic array-based low-power AI accelerators and conducts testing through their functional paths. Accordingly, it can achieve 100% test coverage for both stuck-at and transition-delay faults with a minimal number of test patterns. Additionally, the proposed test architecture requires negligible area overhead since only one AND gate is implemented for the entire systolic array in low-power AI accelerators.

To reduce the cost of memory production, built-off self-test (BOST) enables low-speed automatic test equipment to test the high-speed memory. To maximize the cost reduction benefit of BOST, it is crucial to test as many memories as possible using as few test output pins as possible. For this purpose, a new pipelined output data reducer called PODR is proposed for the output data reduction, and channel sharing between memories tested in parallel is introduced. The proposed structure is adopted to reduce hardware complexity while facilitating test output channel sharing between concurrently tested memories. Additionally, further output data reduction can be achieved by integrating the output data code into the pipelined structure. Output data reduction is also attainable by transmitting fault cell addresses using relative distance from the previously detected fault cells rather than the absolute addresses. Reducing the total code length can be achieved by the adoption of relative addressing, but this requires additional code transmission as its overhead. To mitigate this overhead, a revised approach to relative addressing is introduced. Consequently, as the number of memories tested in parallel increases, the amount of output data of PODR decreases and the number of normalized test output pins usages is reduced in half compared to the previous works.

The increase in memory cell density and capacity has resulted in more faulty cells, necessitating the use of redundant memory row and column lines for repairs. However, existing redundancy analysis (RA) algorithms face a critical issue that RA time increases exponentially with the number of faulty cells. Furthermore, RA solutions for multiple memory chips cannot be derived simultaneously. In this study, a novel RA method is proposed using a convolutional neural network (CNN). The proposed RA algorithm also includes preprocessing to improve training accuracy. The solution locations on the fault map are predicted using multi-label classification. Moreover, parallel solution decision methods ensure that even if the CNN does not find the correct RA solution, an accurate final solution can still be derived, and PyCUDA is used to process multiple memories in parallel. From the experimental results, the normalized repair rate of the proposed RA is 100%. The RA time of the proposed RA is not affected by the number of faults but rather by the CNN execution time. Moreover, RA solutions for multiple memories can be quickly derived simultaneously by utilizing GPU parallel processing. In conclusion, a high yield and low test cost can be achieved.

High bandwidth memory (HBM) represents a significant advancement in memory technology, requiring quick and accurate data processing. Built-in self-repair (BISR) is crucial for ensuring high-capacity and reliable memories, as it automatically detects and repairs faults within memory systems, preventing data loss and enhancing overall memory reliability. The proposed BISR aims to enhance the repair rate and reliability by using a content-addressable memory structure that operates effectively in both offline and online modes. Furthermore, a new redundancy analysis algorithm reduces both analysis time and area overhead by converting fault information into a matrix format and focusing on fault-free areas for each repair solution. Experimental results demonstrate that the proposed BISR improves repair rates and derives a final repair solution immediately after the test sequences are completed. Moreover, hardware comparisons have shown that the proposed approach reduces the area overhead as memory size increases. Consequently, the proposed BISR enhances the overall performance of BISR and the reliability of HBM.

Logic diagnosis is essential for improving reliability and yield. In conventional diagnosis methods, although various methods are proposed to enhance the accuracy and resolution of logic diagnosis, there are still diagnosis results where the reported locations of defects are incorrect. Particularly in logic circuits, which contain a large number of gates, multiple faults can occur, not just single faults. Since the number of possible cases for multiple faults is significantly greater compared to single faults, the diagnosis of multiple faults is complicated. To address this problem, a new diagnosis method that uses a multistage process with fault candidate reduction is proposed. In the proposed method, machine learning is used with fault candidate reduction, and post-processing is performed after the use of machine learning. This proposed method allows for the analysis of multiple faults using only the test responses for single faults, demonstrating that this method can maintain sufficient accuracy and resolution for unexpected faults.

With the rapid advances in artificial intelligence (AI), the demand for data-intensive analytics has surged. Consequently, extensive research on AI acceleration has been conducted to enhance AI performance. Processing-in-memory (PiM) has emerged as a promising AI acceleration architecture, offering an unprecedented high-bandwidth connection between compute and memory. However, integrating many components in PiM can lead to yield degradation. To address this issue, we propose an efficient test architecture that utilizes a hybrid built-in self-test (BIST) for PiM. This architecture utilizes the structural and operational characteristics of PiM to facilitate testing. It can execute testing through the existing functional paths without requiring any additional hardware implementation in PiM. Furthermore, it achieves a 100% test coverage with the small number of test patterns. In addition, the functionality of self-test can be realized for PiM through reconfiguration of the existing hardware, resulting in a very small area overhead.

An algorithmic pattern generator (ALPG) has been developed within automatic test equipment (ATE) due to the extensive number of test patterns required for testing the memories. Since shared-resource ALPG generates the test pattern using the same arithmetic instruction and timing across multiple input/output (I/O) pins, the maximum operating frequency is limited by the delay of the arithmetic operation. On the other hand, per-pin ALPG can achieve high-speed operations by generating one bit of the test pattern for each I/O pin. However, the hardware cost is significantly increased due to the need for individual instruction and pattern generator (PG) for each I/O pin. To address these limitations, a cost-effective per-pin ALPG for high-speed memory testing is proposed. The proposed per-pin ALPG can achieve high-speed operations, and the hardware resources for storing and decoding the instructions are shared among multiple I/O pins to reduce the hardware cost. The experimental results indicate that the proposed ALPG can achieve a higher speed than the conventional per-pin ALPG with a reasonable hardware cost comparable to the conventional shared-resource ALPG.

The rapid increment of the memory density leads to an increment of fault occurrence in memory cells. To improve the memory yield, effective memory test and repair methodologies for automatic test equipment (ATE) have been studied. Multiple memory chips are tested simultaneously by the ATE to improve throughput and reduce costs. In general, redundancy analysis (RA) is used for memory repair. However, since conventional RA methods store fault information in the respective failure bitmaps and operate sequentially, those have limitations due to the high area and analysis time. To address these problems, a novel graphic processing unit (GPU)-based RA method has been proposed which significantly enhances the efficiency of searching for repair solutions for multiple memories. The proposed RA method strategically focuses on the pivot line to efficiently utilize parallel processing and reduce the solution search space. Moreover, the proposed method does not require the extensive use of failure bitmaps since all process is conducted on the GPU. The process involves real-time fault collection, analysis, spare allocation, and solution decision process dynamically during the memory test. Experimental results demonstrate that the performance of the proposed RA method achieves an optimal repair rate and high analysis speed for multiple memories.

Memory test and repair has been generally applied to improve memory yield. However, due to the high cost of automatic test equipment (ATE) equipment, which has been employed for memory test and repair, there is a significant focus on reducing the ATE expense. One of the major problems, which contribute to the increase in ATE cost, is fail address memory. The size of fail address memory, where memory fault information is stored during the memory test, has continuously grown in line with the memory capacity increase. To address the problem, a new fail address memory architecture for cost-effective ATE is proposed in this article. In the proposed architecture, memory fault information is compressed and unrequired memory fault information is eliminated. In addition, a new structure of fail address memory is used to efficiently store memory fault information. Accordingly, the size of fail address memory is highly reduced in the proposed architecture. Furthermore, since some information, which can be used during the memory repair, can be collected during the memory test, the redundancy analysis time required to find memory repair solutions is also reduced in the proposed architecture. The advantages were verified experimentally.

Various memory repair methodologies based on redundancy analysis (RA) have been developed to improve the memory yield. However, conventional RAs often encounter difficulties in finding repair solutions for cases involving a large number of faults and redundancies. To address this problem, an efficient graphics processing unit (GPU)-based RA is proposed using Parallel evaluation for cross faults (GRAP). GRAP involves a preprocessing stage during memory testing, leveraging the parallel processing capacities of the GPU. Preprocessing facilitates rapid solution search by analyzing the fault information. After the test, the solution search is performed. The GPU threads are used to implement all possible cases of redundancy allocation, focusing on cross faults. The remaining faults are categorized by allocating the corresponding redundancies using an efficient method. Given that the solution search process efficiently exploits the multiple threads, GRAP can rapidly find a solution even in cases with a large number of faults and redundancies. Experiments are performed using the compute unified device architecture (CUDA) library for GPU parallel processing, and the performance of the GRAP is compared with those of conventional RA methodologies. The results demonstrated that the proposed RA method can achieve an optimal repair rate with a high analysis speed by leveraging efficient parallel computing.

As fault occurrence probability has increased with corresponding increases in memory density and capacity, memory test and repair have been widely used. However, the total cost for these has increased dramatically due to the increased cost of automatic test equipment (ATE) and the time required for redundancy analysis (RA). The increase in ATE cost has been caused by the increased size of fail address memory, where memory fault information is stored during memory test. The RA time has also increased because the difficulty encountered during fault analysis has increased in proportion to the increase in the number of memory faults. To address these problems, an RA-aware fail data collection architecture is proposed. This includes a new fail address memory structure that can significantly reduce the fail address memory size. Moreover, the architecture can integrate memory fault information using simple calculations without any data losses. In addition, unnecessary memory fault information can be eliminated easily with efficient data encoding to reduce the data size. Furthermore, since some information required for fault analysis in memory repair can be collected during memory test, the RA time needed to find memory repair solutions is also reduced without any degradation in the repair rate. Consequently, the total cost for memory test and repair can be considerably reduced by reducing the cost of ATE and the RA time. Experimental results reveal that the fail address memory size and RA time can be reduced by an average of 63% and 41%, respectively, with the proposed architecture.

The increasing demand for data-intensive analytics, driven by the rapid advances in artificial intelligence (AI), has led to the proposal of various AI accelerators. However, as AI-based solutions are being applied to applications that require high accuracy and reliability, ensuring the dependability of these solutions has become a critical issue. In this brief, we present an area-efficient systolic array redundancy architecture for reliable AI accelerator. In the proposed architecture, computations assigned to faulty multiply-accumulate (MAC) units are bypassed using dedicated routes. Subsequently, the same computations are executed in shiftable redundant MACs or selectable redundant MACs. This ensures the correct completion of calculations all without performance reduction. Moreover, the reassignment of computations can be efficiently managed through a simple scheduling algorithm. As a result, the proposed architecture achieves a high repair rate through the redundant MACs and effective computation reassignment. Despite these capabilities, the proposed architecture incurs only a small area overhead.

As the demand for data-intensive analytics has increased with the rapid advance in artificial intelligence (AI), various AI accelerators have been proposed. However, as AI-based solutions have been adapted to applications requiring accuracy and reliability, the reliability of them has become a critical issue. For this reason, self-test and self-recovery for AI accelerator (STRAIT) is proposed in this article. It facilitates self-test, self-diagnosis, and self-recovery by utilizing the structural and operational characteristics of systolic array in AI accelerator. The proposed self-test is progressed using scan chains composed of functional paths and can achieve a 100% test coverage (for both stuck-at and transition-delay faults) with a small number of test patterns and reduced test power. The proposed self-diagnosis is progressed with the proposed self-test in real time and allows accurate fault localization with fault type analysis. The proposed self-recovery is progressed using efficient pruning for faulty processing elements with weight allocation, and the reliability of AI accelerators can drastically increase with negligible performance degradation. However, STRAIT can be implemented with a small area overhead.

To address the demand for memory scaling capabilities, 3-D integrated circuits (3D-ICs) based on short and dense through-silicon vias (TSVs) have been introduced. However, the defects of TSVs considerably influence the yield and reliability of 3D-ICs. For this reason, TSV repair using switch matrix (SM) topology (TRUST) is proposed in this article. TRUST adopts an SM, which has a high routing flexibility, to realize TSV connections. Consequently, a 100% repair rate can be achieved for the 3D-ICs that have faulty TSVs smaller than or equal to redundant TSVs. Furthermore, TRUST utilizes content-addressable memories in built-in self-repair to identify TSV repair paths via a simple TSV repair path search algorithm. For this reason, TRUST can be applied to repair manufacturing and aging defects of TSVs. Nevertheless, TRUST can be applied with reasonable area and delay overheads, such as 58.3% area reduction and 55.1% delay reduction compared to the only conventional TSV repair architecture that can achieve the optimal repair rate. In addition, the area ratios in high bandwidth memory (HBM) and HBM2 are only 5.3% and much smaller than 0.1%, respectively. The advantages are experimentally verified.

With technological advancements, the density and capacity of memory are rapidly increasing. As the number of memory cells increases, the difficulty of fault analysis and the number of faults also increase. Hence, the yield and test cost of memory have become essential issues in memory manufacturing. Many manufacturers have used redundancy analysis (RA) to improve the memory yield and decrease the test cost. However, most conventional RA methods require a lengthy analysis time to find a repair solution, and it is difficult to obtain an optimal repair rate with conventional RA algorithms. Although several algorithms using various spare structures to achieve performance improvement have been proposed, those improvements have not been ground breaking. In this article, a new multibank optimized RA (MORA) algorithm is proposed. It achieves a very high repair rate and a drastic reduction in the analysis time compared with conventional RA algorithms using various spare structures. During testing, the proposed algorithm stores the faulty cell information efficiently. Therefore, the analysis time can be shortened through the presolution process of the repair analysis using the proposed fault storage spaces. Additionally, the proposed spare structures are used to increase the repair rate. The experimental results reveal that the proposed algorithm can achieve a very high repair rate at a faster speed than conventional RA algorithms.

Advances in the density and capacity of dynamic random access memories (DRAMs) have resulted in emerging reliability issues. The error correction code (ECC) is widely used as a promising technique to improve the reliability of high-density memories. For this reason, many studies on ECC have been conducted to address the increased cell failure rates. However, conventional ECCs have shown limited achievements owing to area, latency, and power overheads. This study proposes ECC architecture reusing content-addressable memories (CAMs) for obtaining high reliability in DRAM, which can be called ECMO. The proposed architecture reuses CAMs in built-in self-repair, which can be used to repair memory hard faults during manufacturing as data storage to replace error data words. This achieves high reliability along with an additional 9155 h DRAM lifetime. Nevertheless, it can be implemented with a 3.04% area overhead due to the reuse of CAMs. Moreover, only 0.21 ns is added to the critical path. Furthermore, the power overhead is 0.1% compared to the total power consumption of DDR3 and DDR4.

Since the probability of fault occurrence on memory has increased with the advance of memory density and capacity, memory repairs in wafer-level and package-level are widely used with redundancy analysis (RA) to improve memory yield. However, as the costs for memory repair also have increased in proportion to the memory density and capacity, the repair costs have occupied a significant portion of the total costs. To address the problem, one-time memory repair with wafer-level early repair analysis (W-ERA) for cost reduction is proposed in this paper. The proposed W-ERA facilitates that all unrepairable memories are classified rapidly without searching memory repair solutions in wafer-level and repairable memory faults occurred in wafer-level are repaired in package-level with additional faults occurred in package-level simultaneously. It means, as the costs of memory repair can be highly reduced since memory repair is skipped in wafer-level, the total costs also can be highly reduced. In addition, memory redundancies can be efficiently used for memory repair in package-level and it results a high repair rate achievement.

Since the redundancy analysis (RA) has been introduced for memory yield, many RA researches have been conducted. However, objective comparisons of them are difficult by the absence of real memory models with realistic fault distributions. This paper presents a fail memory configuration set for RA estimation, called as ITC'2020 RA Benchmarks. It enables objective estimations of RAs with respect to effectiveness and efficiency. The fail memory configuration set includes memory models which have various redundancy structures and a fault generation algorithm with fault distribution which can be criteria for objective comparisons of RA. Simulations for estimations and comparisons of RA researches including BIRA are progressed utilizing the fail memory configuration set.

Redundancy analysis (RA) is essential for improving memory yield. The recent increase in memory size has made RA more complicated. This article presents graphics processing unit (GPU)-based RA using concurrent evaluation (GRACE), which is an efficient RA technique. In GRACE, to perform dynamic RA, memory faults found during the test are directly analyzed instead of being stored in the fault bitmap in the automatic test equipment (ATE). Therefore, RA is performed simultaneously with the memory test, and the RA latency is eliminated after the test time. Using the GPU, all possible repair cases are examined in parallel; thus, a high memory repair rate is achieved in a short period of time. Also, GRACE can be applied to practical environments where the structure of memory redundancy is complicated. Experimental results indicate that GRACE is faster than other ATE-based RA methods since it completes the RA almost simultaneously at the end of the test. Additionally, the repair rate of GRACE is always higher than those of the other RA methods.

As advances in memory density and capacity result in an increase in the probability of fault occurrence, many studies on built-in redundancy analysis (BIRA) have been conducted to address this problem. However, conventional BIRAs cannot directly find a final repair solution as soon as test sequences of the built-in self-test (BIST) are over, because they require starting the fault analyses after finishing the test sequences to achieve an optimal repair rate. For this reason, additional analysis time is inevitable, which affects total test costs. In this paper, a dynamic BIRA is proposed for memory repair. It can find a final repair solution directly as soon as test sequences if the BIST are over and achieve an optimal repair rate. The proposed BIRA can restore faults in fault-storing content-addressable memories whenever the spaces in them can be reduced via dynamic fault analysis. Furthermore, the proposed BIRA can be implemented with a reasonable hardware size. This is demonstrated via experiments.

With the development of memory manufacturing technology, the density of memory die has been increased and more data can be stored in a small area than before. However, due to the complexity of the manufacturing process, faults in memory have increased. And it leads to poor yield and quality of memory. To improve yield and quality of the memory, the importance of memory test and repair is growing to maintain memory productivity. This paper presents solutions for test and repair in pre-bond. In the pre-bond, proposed method makes a new 3D stacked memory by using unrepairable memory dice which cannot be repaired with existing spare memories. Discard the bank with the largest number of faults in the unrepairable memory die and repair the remaining banks. The memory dice and a spare layer which made of the known good die or unrepairable memory die are stacked to create a 3D memory. A bank of the spare layer is mapped to discarded bank of unrepairable memory die to operate as one normal working memory die. The proposed method can lead to high yields of 3D stacked memory.

Advances in memory density and capacity have had the consequence of increasing the probability of memory faults. For this reason, redundancy analysis (RA) and repair are used as effective solutions to improve memory yield. However, as the growth of the number of memory cells increases, it causes increase of the number of faulty cells and results in increase of difficulty of fault analysis. Although various RA methodologies have been proposed, most of them require a long analysis time or fast analysis speed without achieving a 100% normalized repair rate. Furthermore, research on conventional RA methodologies has not included effective early termination methods. Therefore, in this paper, fault group pattern matching (FGPM) is proposed for high speed RA with an effective early termination method. It can achieve very fast analysis with a 100% normalized repair rate. Additionally, it can finish the analysis rapidly by the proposed early termination method when a memory cannot be repaired. Experimental results demonstrate that the FGPM is highly effective in reducing analysis time with the achievement of a 100% normalized repair rate. In addition, the effectiveness of the proposed early termination is shown.

Built-in redundancy analysis (BIRA) is widely used for memory yield improvement. However, increases in fault occurrence probability inevitably lead to the use of various spare lines to achieve a high repair rate. Generally, it is difficult to apply conventional BIRAs for memories with various spare lines because they focus on a simple spare structure. Therefore, this study examines a BIRA that focuses on a various spare lines structure. The proposed BIRA achieves a high repair rate through the use of various spare lines. Although long analysis time is typically required due to the use of various spare lines, the proposed BIRA solves the problem through sequential spare line allocation. Additionally, it achieves hardware overhead reduction through a simple analyzer. These advantages of the proposed BIRA are demonstrated experimentally.

The growing capacity and density of embedded memories increases the probability of defects and affects the yield. To improve the yield, built-in redundancy analysis (BIRA) has been developed to replace faulty cells with healthy redundant cells. BIRA requires a high repair rate and a feasible hardware size for implementation. Although many BIRAs have been proposed, most of them still demonstrate a low repair rate or a large required hardware size. The proposed BIRA employs an intuitive algorithm with a small-area analyzer that uses 1-D spare segments in the 2-D spare structure. Because most faults in the memory are single faults, spare segments can be used to efficiently allocate redundancies. In terms of the yield, 1-D spare segments are effective when used with an intuitive algorithm that can be implemented with a small hardware overhead. Experimental results show that the proposed BIRA has a higher repair rate and relatively low hardware overhead than state-of-the-art BIRAs and has the advantages of 1-D spare segments.