Demo Data from VLDB 2026 / reviewers in the wild / expert
Szu-Yuan Han
dblp:159/9427
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 2017
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design › placement
detailed placement |
0.2 | 1 | 2015 | On Refining Row-Based Detailed Placement for Triple Patterning Lithography · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015 |
Electronic design automation › physical design
lithography |
0.2 | 1 | 2015 | On Refining Row-Based Detailed Placement for Triple Patterning Lithography · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015 |
Electronic design automation
physical design |
0.2 | 1 | 2015 | On Refining Row-Based Detailed Placement for Triple Patterning Lithography · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015 |
Electronic design automation › physical design › lithography
triple patterning lithography |
0.2 | 1 | 2015 | On Refining Row-Based Detailed Placement for Triple Patterning Lithography · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015 |
Methods — techniques the papers use, named apart from their topics
white space insertion · 0.2shortest path algorithm · 0.2cell flipping · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2017 | Delay-driven layer assignment for advanced technology nodesabstractThis paper addresses a delay-driven layer assignment problem with consideration of via delay and coupling effect in the global routing stage. A negotiation-based framework is proposed to balance delay, congestion, and via count. Coupling capacitance is considered using a probabilistic look-up table. Finally, the proposed algorithm uses both parallel wires and wide wires to reduce wire delay. The effectiveness of our layer assignment algorithm is supported by extensive experimental results. Szu-Yuan Han, Wen-Hao Liu 0001, Rickard Ewetz, Cheng-Kok Koh, Kai-Yuan Chao, Ting-Chi Wang |
ASP-DAC | 1 |
| 2015 | A Cell-Based Row-Structure Layout Decomposer for Triple Patterning LithographyabstractIn this paper, we study a cell-based row-structure layout decomposition problem for triple patterning lithography (TPL) which asks to minimize a weighted sum of coloring conflicts and stitches. We show how to extend a prior graph-based approach to solve the problem optimally under certain assumptions. Furthermore, several methods to substantially reduce the graph size and hence to accelerate the extended approach are presented. Experimental results show that our decomposer can significantly outperform a state-of-the-art work in terms of both solution quality and run time. Hsi-An Chien, Szu-Yuan Han, Ye-Hong Chen, Ting-Chi Wang |
ISPD | 2 |
| 2015 | On Refining Row-Based Detailed Placement for Triple Patterning LithographyabstractIn this paper, we study row-based detailed placement refinement for triple patterning lithography (TPL), which asks to find a refined detailed placement solution as well as a valid TPL layout decomposition under the objective of minimizing the number of stitches and the half-perimeter wirelength. Our problem does not have precoloring solutions of cells as the input, and it allows using techniques, including white space insertion, cell flipping, adjacent-cell swapping, and vertical cell movement, to optimize the solution quality. We first present (resource-constrained) shortest-path-based algorithms for several TPL-aware single-row placement problems that allow or disallow perturbing a given cell ordering. Based on these algorithms, we then propose an approach to our TPL-aware detailed placement refinement problem, which first minimizes the number of stitches and then minimizes the wirelength. Finally, we report extensive experimental results to demonstrate the effectiveness and efficiency of our approach. Hsi-An Chien, Ye-Hong Chen, Szu-Yuan Han, Hsiu-Yu Lai, Ting-Chi Wang |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |