This paper presents an algorithm for probabilistic analysis of the power dissipation in switched-capacitor circuits, which are frequently found in a number of low-power designs, such as those for mobile communications equipment. The inputs to the circuit are modeled as a stationary Markov process of order zero or one. The expected power dissipation is obtained from first- and second-order moments of (he probability distributions of voltages and charges in the circuit. The algorithm does not require Monte Carlo analysis; instead, (he moments of the probability distributions are computed from the solutions of systems of linear algebraic equations, taking into account any correlation among the inputs. To demonstrate the algorithm's performance, numerical results obtained on a number of sample switched-capacitor circuits are reported.

Many mixed-technology and mixed-signal designs require the assessment of the system's performance in the presence of signals that are best characterized as having continuous frequency spectra: for instance, the simulation of a circuit's behavior in the presence of electrical noise. This paper describes an algorithm for frequency-domain simulation of nonlinear systems capable of handling signals with continuous spectra. The algorithm is based on an orthogonal series expansion of the signals in the frequency domain. Thus it is, in a sense, the dual approach to frequency-domain simulation with respect to harmonic balance, which relies on a time-domain series expansion of the signals. Signal spectra are obtained from the solution of a system of nonlinear algebraic equations whose dimension increases with the desired spectral accuracy. Numerical results obtained on an optical amplifier are presented.

The total power dissipation in a switched-capacitor circuit can be expressed as the sum of two terms: the static power absorbed by the operational amplifiers and the switching power, i.e., the power dissipated in charging and discharging the capacitors. It is shown that, in general, the switching power depends on the order in which the switches connected to the same clock phase are closed. In practice, it is impossible to know this order with absolute certainty. As a consequence, a realistic estimate of the power dissipation can only be given as a range of possible values. It is shown that upper and lower bounds on the power dissipation can be computed by solving a single-source shortest paths problem on a directed graph. Numerical results obtained on a number of switched-capacitor circuits indicate that, if low-power operational amplifiers are used, the switching power can be a significant fraction of the circuit's overall power dissipation.

This paper describes an algorithm for the efficient solution of large systems of Boolean equations. The algorithm exploits the fact that, in some cases, the composition operation of Boolean functions represented by BDD's can be performed in a very efficient manner. Thus, the algorithm tries to eliminate as many variables and equations as possible through function composition. When the system can no longer be reduced in this way, the elimination process is continued through the use of Shannon decomposition. Numerical results show that the performance of this algorithm is significantly superior to that of a previous algorithm proposed by the authors.

A number of low-power designs, such as those for mobile communication equipment, contain switched-capacitor circuits. In such designs it is important to be able to estimate the power dissipated by the switched-capacitor portion of the circuit. This paper describes an algorithm for the computation of statistical information about the power dissipated in a switched-capacitor circuit when corresponding statistical information about the inputs to the circuit is known. Ordinary circuit simulators are not suited for this task. Because they can only compute the power dissipated by the circuit for one specific set of input signals. The algorithm does not require Monte-Carlo analyses, and it accounts for correlation among the inputs. To demonstrate the algorithm's performance, numerical results obtained on a number of sample switched-capacitor circuits are reported.

This paper describes an algorithm for the simulation of gate-level logic. Multiple logic levels are used to describe the state of each node. Each state corresponds to a different voltage level, and the number of levels to be used for a simulation is user-defined. This feature simplifies considerably the interface between a digital and an analog simulator. A DC solver is incorporated to find the initial operating point of a circuit before a transient analysis begins. This solver has the capability of finding the operating point of gates located in feedback loops. For transient analysis, a gate delay model that takes into account the slope of the input waveforms is used. The performance of the algorithm is demonstrated by simulations of a number of benchmark circuits.

The trend towards integration of analog and digital components on the same chip is creating a need for simulators capable of handling high-level analog behavioral models. This paper presents a multi-level simulation algorithm that accepts analog behavioral models written in the C programming language. The portions of the circuit described at the behavioral level are treated as if they were individual devices with their own stamps. There are two main advantages to this approach: on one hand, it creates a seamless environment where there is no need to use different algorithms to simulate different parts of the same circuit. On the other hand, the proposed algorithm gets around the problem of having to come up with a reliable and efficient way to differentiate the behavioral equations, because the stamps for the elements described at the behavioral level are generated using Broyden's method, which does not require evaluation of derivatives. Numerical results show that the algorithm offers a viable, efficient approach to multi-level analog simulation.>

A macromodel is an electrical network containing fewer devices and/or fewer nodes than the circuit it represents. A general-purpose algorithm for the generation of macromodels suitable for circuit simulation is presented. The algorithm is based exclusively on a comparison of the input-output behavior of the macromodel with that to the circuit to be modeled. Because no reliance on any particular properties of the circuit is made, the algorithm can be used to model a very wide class of circuits. Three examples are presented to demonstrate the algorithm's performance, two of which were chosen specifically to test the algorithm's ability to approximate nonlinearities in the circuits to be modeled. In all cases, the accuracy of the macromodels was shown to improve substantially using reasonable amounts of CPU time.>

The term aggregation denotes a class of methods that were originally conceived as a way to compute an approximate solution of a linear system of equations. It has been shown that they could be used to accelerate the convergence of linear relaxation algorithms. Although all aggregation methods rely on the same general idea, each individual method is usually based on a heuristic that is valid for a particular class of problems. It is shown how the idea behind these methods can be generalized to include nonlinear equations, and a number of theorems concerning their theoretical properties are proven. How their performance in the linear case can be significantly improved if the heuristic approach is abandoned in favor of a rigorously mathematical one is shown. As a practical test, numerical results obtained on a number of matrices resulting from common problems in computer-aided design of integrated circuits are presented.>