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Pierre Azéma

dblp:16/2684 · DBLP profile ↗
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9ranked-venue papers
4as first author
0since 2021 · last 2001
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 1 first-authorSoftware engineering, systems software and programming languages · 3 · 3 first-authorComputer networks · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Distributed systems · 37% Electronic design automation · 35% Hardware reliability and fault tolerance · 24%
Software engineering, system software, and programming languages
2 papers
Program verification · 100%

Topics — the 10 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Program verification
distributed system verification
0.011984
Specification and Verification of Distributed Systems Using PROLOG Interpreded Petri Nets · ICSE 1984
Distributed systems
distributed system specification
0.011984
Specification and Verification of Distributed Systems Using PROLOG Interpreded Petri Nets · ICSE 1984
Electronic design automation › design representation
petri net specification
0.011984
Specification and Verification of Distributed Systems Using PROLOG Interpreded Petri Nets · ICSE 1984
Hardware reliability and fault tolerance › functional safety
fail-safe systems
0.011979
Unified Design of Self-Checking and Fail-Safe Combinational Circuits and Sequential Machines · IEEE Trans. Computers 1979
Distributed systems
fault tolerance
0.011979
Unified Design of Self-Checking and Fail-Safe Combinational Circuits and Sequential Machines · IEEE Trans. Computers 1979
Hardware reliability and fault tolerance
self-checking circuits
0.011979
Unified Design of Self-Checking and Fail-Safe Combinational Circuits and Sequential Machines · IEEE Trans. Computers 1979
Program verification
protocol verification
0.011978
Design and Verification of Communication Procedures: A Bottom-Up Approach · ICSE 1978
Electronic design automation › hardware verification and test
hardware verification
0.011976
Petri nets as a common tool for design verification and hardware simulation · DAC 1976
Integrated circuit design
digital circuit design
0.011979
Unified Design of Self-Checking and Fail-Safe Combinational Circuits and Sequential Machines · IEEE Trans. Computers 1979
Electronic design automation
hardware simulation
0.011976
Petri nets as a common tool for design verification and hardware simulation · DAC 1976

Methods — techniques the papers use, named apart from their topics

petri nets · 0.0prolog · 0.0APL simulation · 0.0
YearPublicationVenuePosition
2001 Testability analysis in communicating systems
Khalil Drira, Pierre Azéma, Pierre de Saqui-Sannes
Comput. Networks2
1994 Distributed Coin Tossing
abstract
This paper presents algorithms for distributed coin tossing. Distributed coin tossing furnishes a symmetrical way to break the symmetry in a distributed system. They allow the conflicts arising from competing remote sites to be overcome in a fair (equiprobable) manner: any site has an equal chance of being selected. It as also shown how these algorithms may be used to obtain a total order between competing sites of a system. Moreover, in each case the outputs of our algorithms are totally unpredictable.>
François Vernadat 0001, Pierre Azéma, Khalil Drira
ICDCS2
1993 A Formal Assessment of Synchronous Testability for Communicating Systems
abstract
A testability assessment approach for multicomponent systems is proposed within the framework of formal description techniques. The approach relies on the formal definition of implementation conformance with respect to a given specification. It provides measures of user confidence and guidelines for an automatic design analysis. Both items are based on test requirements. The proposed technique for testability assessment formalizes the common-sense statement that testability of a component is degraded when this component cannot be tested in isolation. Furthermore, it gives a precise answer to the question: What are the limits of a test taking into consideration the constraints of a given environment?.>
Khalil Drira, Pierre Azéma, B. Soulas, A. M. Chemali
ICDCS2
1990 A Bus Instrumentation Protocol Specified in LOTOS
Pierre Azéma, Khalil Drira, François Vernadat 0001
FORTE1
1986 On a Prolog Environment for Protocol Analysis
Giorgos Papapanagiotakis, Pierre Azéma, Brigitte Pradin-Chezalviel
ICDCS2
1984 Specification and Verification of Distributed Systems Using PROLOG Interpreded Petri Nets
Pierre Azéma, G. Juandle, E. Sanchis, M. Montbernard
ICSE1
1979 Unified Design of Self-Checking and Fail-Safe Combinational Circuits and Sequential Machines
abstract
This correspondence deals with a unification and extension of some previous work on self-checking (SC) and fail-safe (FS) systems.
Michel Diaz, Pierre Azéma, Jean-Michel Ayache
IEEE Trans. Computers2
1978 Design and Verification of Communication Procedures: A Bottom-Up Approach
Pierre Azéma, Jean-Michel Ayache, Bernard Berthomieu
ICSE1
1976 Petri nets as a common tool for design verification and hardware simulation
abstract
An APL simulation is developped in the case of parallel systems which communicate with the environment. This method using interpreted PETRI nets, helps the design verification.
Pierre Azéma, Robert Valette, Michel Diaz
DAC1