The Smart Grid concept evolved from the idea of intelligent and secure management of electrical grid infrastructure components and their communication through sustainable integration with the state-of-the-art technologies. This research focuses on emerging quantum computing-assisted security and its application in the Smart Grid. The robustness of electrical grid is increasing every day through advancements in grid infrastructure management which include outage control, relay protection, reliable distribution, renewable energy resource integration, and energy trading. Quantum Computing emerges as a formidable solution for application in the smart grid due to its processing capability and scale. Its application and scope are evolving every day with the recent developments in Quantum Chips which could pave the way for emerging Quantum-Chain-of-Things (QCoT). This research focuses on providing robust security in smart grids through Quantum Physical Unclonable Functions (QPUF) primitive, a quantum-hardware assisted security approach driven by micro manufacturing quantum process variations for generating a quantum digital fingerprint driven by quantum mechanics principles. The QPUF experimental evaluation in this research was performed to uniquely fingerprint various electrical grid entities providing a sustainable and secure flow of communication. Experimental evaluation shows a robust and reliable extraction of quantum digital fingerprints from noisy IBM quantum systems. The evaluation shows an impressive 86% keys achieving 100% reliability.

Sustainable advancement is being made to improve the efficiency of the generation, transmission, and distribution of renewable energy resources, as well as managing them to ensure the reliable operation of the smart grid. Supervisory control and data acquisition (SCADA) enables sustainable management of grid communication flow through its real-time data sensing, processing, and actuation capabilities at various levels in the energy distribution framework. The security vulnerabilities associated with the SCADA-enabled grid infrastructure and management could jeopardize the smart grid operations. This work explores the potential of Quantum Physical Unclonable Functions (QPUF) for the security and reliability of the smart grid’s energy transmission and distribution framework. Quantum computing has emerged as a formidable security solution for high-performance computing applications through its probabilistic nature of information processing. This work has a quantum hardware-assisted security mechanism based on intrinsic properties of quantum hardware driven by quantum mechanics to provide tamper-proof security for quantum computing-driven smart grid infrastructure. This work introduces a novel QPUF architecture using quantum logic gates based on quantum decoherence, entanglement, and superposition. This generates a unique bitstream for each quantum device as a fingerprint. The proposed QPUF design is evaluated on IBM and Google quantum systems and simulators. The deployment on IBM quantum (ibmq_qasm_simulator) and Google Cirq simulators has achieved 100% reliability with an average Hamming distance of 50.07%, 51% randomness.

Physical Unclonable Functions (PUFs) are widely researched in the field of security because of their unique, robust, and reliable nature, PUFs are considered device-specific root keys that are hard to duplicate. There are many variants of PUFs that are being studied and implemented including hardware and software PUFs. Though PUFs are believed to be secure and reliable, they are not without challenges of their own. The efficient performance of PUF depends on various environmental factors, which leads to inefficiency. Bit flipping is one such problem that can bring down the reliability of the PUF. Memory-based PUFs are prone to unavoidable bit flips occurring in the hardware, similarly, sensor-based PUFs are prone to bit flips occurring due to temperature variation. The number of errors in the PUF response must be minimized to improve the reliability of the PUF in security applications. In this research we explore the Machine Learning (ML) model based on K-mer sequencing to detect and correct the bit flips in the PUFs, hence fortifying the PUF-based secure authentication system for authentication and authorization of Edge Data Centers (EDC) in a Collaborative Edge Computing (CEC) Environment.

Deepfake has emerged as a threat to individual’s privacy and identity. It uses advanced deep learning algorithms to synthesize visual, text, and audio from multimedia content in a realistic way. The advancement of Deepfake techniques is posing a question on the integrity of the digital content on social media. This work presents a novel hardware assisted Deepfake mitigation approach through the device and content integrity verification. In this work, the potential of hardware security primitive Physical Unclonable Functions (PUF) for mitigation of visual Deepfakes has been explored. The proposed framework presents a novel PUF-based image attestation technique that uses human facial features to create a unique pseudo-identity. The proposed architecture maps facial key point coordinates of each person in an image to PUF and creates a unique PUF generated key thereby having a unique pseudo identity for each image. Experimental evaluation uses Dlib facial detection model for facial attribute extraction and uses Arbiter PUF for image attestation.

Billions of devices on the Internet of Things (IoT) capture massive amounts of data from everyday events, raising privacy and security concerns. The current technology standard transfers the majority of this data over the internet stores it, processes it, and uses it to train machine learning (ML) and deep learning (DL) models on the cloud server. Then, edge devices make decisions. However, this threatens data privacy and security. Federated learning (FL) can be helpful in this scenario because it transfers the model to the data. However, issues like poor network connectivity, low bandwidth, and network latency demand more research on edge-based models, on-device training, and lightweight and low-overhead communication protocols. In this article, we present ToEFL, an incremental training (T) on (o) edge (E) method for an FL network in a smart agriculture application, addressing data bottlenecks and low computational capability constraints. We selected plant disease detection as the application. The whole idea is to train the model on the edge device to reduce the frequency of server updates and make ToEFL suitable for a remote village where internet service may be poor. The ToEFL system can choose between server and local models based on model performance, with the latter more tailored to a local dataset.

Physical Unclonable Functions (PUFs) are widely studied for the security of devices in the largely heterogenous Internet-of-Things ecosystem. The need for low-power and low-cost yet robust and reliable security systems is of prime importance in resource-constrained environments like smart villages. Using PUFs as a security primitive has the limitation of environmental effects that lead to bit flipping in the PUF response, the challenge in using PUFs is to overcome the bit errors without adding to the area overhead or computational overhead. This research proposes a novel bit error detection and correction algorithm implemented using Federated Learning (FL). The error detection and correction model uses the N-gram concept of Natural Language Processing (NLP). The FL model is implemented on Flower AI, the global model gets the locally trained model's parameters, updates itself, and shares the updated models with all the local models. At the edge, the use of FL for model training and updating enhances the efficiency of the authentication system that uses PUF Challenge-Response Pairs (CRPs), reduces the area overhead and power consumption, and improves the security of the PUF-based authentication system.

The increasing threat to individual privacy and personalized digital content on social media posed by Deepfakes has highlighted the importance for a secure and reliable multimedia content integrity mechanism. In this paper a novel Blockchain driven hardware secure video attestation scheme, BlockShield is proposed for Deepfake mitigation. The proposed system includes a novel approach that ensures digital content traceability and privacy using Blockchain smart contracts and TPM's digital signature mechanism. The proposed work explores the scope of hardware-assisted security for Deepfake mitigation through a hardware TPM working together with Blockchain for enhanced digital media protection and sharing. The proposed work is experimentally validated and presented which validates the scope of hardware-assisted and blockchain integrated Deepfake mitigation framework.

Food is crucial in our life. Despite food manufacturers' efforts to meet consumers' needs with manufactured food, it cannot attain the identical level of quality and flavor as natural food. Some fruits and vegetables are classified as food that cannot be manufactured. Also, they play an essential role worldwide. This paper focuses on how farmers can protect their farms from an object that might threaten the crops and cause damage to them. It proposes a framework that farmers may utilize to safeguard the crops against any species of birds. Considering the adverse impact of bird attacks on crop production, this system effectively addresses this problem and consistently enhances the quality and quantity of them. It utilizes computer vision technology to establish a secure environment for the crop. This system is called Quality of Crop Device (qCrop), and it works with a You Only Look Once (Yolov8m) model to detect birds with high accuracy to protect farms.

Collaborative Edge Computing (CEC) works on the distributed model, and is established at the Fog layer that consists of multiple edge devices like Edge Data Centers (EDCs), Edge Routers etc. In the CEC environment, the Edge layer has the capability of storing and processing data. Since the processing capacity is limited, many edge devices collaborate with each other to offload the processing in a scheme called Load Balancing. CEC enables applications in smart villages through task offloading/sharing, which calls for a trusted security system to make the resource sharing and information safe. Since the Edge is a resource-constrained environment where not all data centers are resourceful enough to implement computation intensive security systems. Physically Unclonable Functions (PUF) are a robust, secure, and light-weight solution for providing hard- ware security. PUFs are used to authenticate the EDCs during load balancing in a collaborative edge computingenvironment. Though PUFs are secure and difficult to remodel, the drawback lies in the storage of Challenge-Response Pairs (CRP) in a CRP database. The storage space for the CRP database becomes a concern when many EDCs participate in dynamic load balancing and each EDC needs to store a copy of the database. This research proposes a PUF based certificate Authority protocol for authentication of EDCs which will eliminate the need for CRP database storage while harnessing the security feature of the PUF. Further, in this research the effised authentication system is evaluated through oretical analysis and experimental results.

In smart healthcare, blockchain technology addresses existing concerns with security, privacy, and electronic healthcare records. In addition, utilizing edge devices with IoMT devices is very advantageous for addressing security, computing, and storage challenges. Symmetric and asymmetric keys are used to conceal sensitive information from unauthorized parties. Moreover, the hash function SHA256 helps for data alteration detection. The proposed system uses a blockchain-based smart healthcare system using IoMT devices for continuous patient monitoring. The edge device is used to hash and encrypt data and provide additional computational capability. A symmetric key maintains data privacy in the blockchain, allowing patients to safely share data through smart contracts while preventing unauthorized physicians from seeing it. A verification node and blockchain sign and validate patient data in the healthcare provider system using an asymmetric key. Location-based authentication is addressed to ensure the authenticity and data source.

This work presents a sustainable cybersecurity solution using Physical Unclonable Functions (PUF), Trusted Platform Module (TPM), and Tangle Distributed Ledger Technology (DLT) for sustainable device and data security. Security-by-Design (SbD) or Hardware- Assisted Security (HAS) solutions have gained much prominence due to the requirement of tamper-proof storage for hardwareassisted cryptography solutions. Designing complex security mechanisms can impact their efficiency as IoT applications are more decentralized. In the proposed architecture, we presented a novel TPM-enabled PUF-based security mechanism with effective integration of PUF with TPM. The proposed mechanism is based on the process of sealing the PUF key in the TPM, which cannot be accessed outside the TPM and can only be unsealed by the TPM itself. A specified NV-index is assigned to each IoT node for sealing the PUF key to TPM using the Media Access Control (MAC) address. Access to the TPM's Non-Volatile Random Access Memory (NVRAM) is defined by the TPM's Enhanced Authorization policies as specified by the Trust Computing Group (TCG). The proposed architecture uses Tangle for sustainable data security and storage in decentralized IoT systems through a Masked Authentication Messaging (MAM) scheme for efficient and secure access control to Tangle. We validated the proposed approach through experimental analysis and implementation, which substantiates the potential of the presented PUFchain 4.0 for decentralized IoT-driven security solutions.

In this paper a design optimization flow is proposed for memristor-based oscillators using the Gravitational Search Algorithm. This paper presents for the first time a memristor behavioral model in the Simscape physical modeling language. Using this model, a memristor based Wien oscillator is characterized within the Simscape framework. The oscillation frequency and power consumption of the oscillator for different configurations are explored.

With the rapid increase in the chip density, Network-on-Chip (NoC) is becoming the prevalent architecture for today's complex chip multi processor (CMP) based systems. One of the major challenges of the NoC is to design an enhanced parallel communication centric scalable architecture for the on chip communication. In this paper, a hybrid Mesh based Star topology has been proposed to provide low latency, high throughput and more evenly distributed traffic throughout the network. Simulation results show that a maximum of 62% latency benefit (for size 8x8), 55% (for size 8x8), and 42% (for size 12x12) throughput benefits can be achieved for proposed topology over mesh with a small area overhead.

Due to the increasing complexity of nanoscale CMOS circuits and systems integration, full SPICE simulations for silicon accurate results can have run times in the order of days or weeks. This paper presents a methodology that uses a simple Kriging metamodeling technique capable of modeling the correlation effects between parameters, and a simulated annealing algorithm for ultrafast design optimization. The proposed methodology is applied to a clamped bitline amplifier circuit, which shows promising results for increased accuracy in process-aware metamodeling techniques. The error of the metamodels is very small, which is generated in 10.5 min compared to the 72 h taken for an exhaustive simulation. The design optimization performed on the metamodels improves the precharge time of the circuit by 61.15%.

The gap between abstraction levels in analog design is a major obstacle for advancing analog and mixed-signal design automation. Intelligent surrogate models for low-level analog building blocks are needed to bridge behavioral and transistor-level simulations. With this objective, artificial neural network (ANN) metamodels are incorporated in Verilog-AMS to capture the highly nonlinear response of the analog block. Parameterized ANN Verilog-AMS behavioral metamodels are constructed for efficient system-level design exploration. The application of these intelligent metamodels to multi-objective analog block optimization is demonstrated. To the best of the authors' knowledge this is the first paper to integrate artificial neural network models in Verilog-AMS. To demonstrate the application of iVAMS, a biologically-inspired “firefly optimization algorithm” is applied to an OP-AMP design. The optimization process is sped up by 5580× due to the use of iVAMS with negligible loss in accuracy.

An automated top-down design flow to achieve physical design of Analog/Mixed-Signal Systems-on-Chip (AMS-SoCs) is difficult, especially for nano-CMOS. Process variation effects have profound impact on the performance of silicon versus layout design. In this paper metamodels, (surrogate models) and Particle Swarm Optimization (PSO) have been combined in an automated physical design flow for fast design exploration of AMS-SoCs. Neural network based non-polynomial metamodels that handle large numbers of design parameters, are used to predict the statistical process variation effects instead of exhaustive Monte Carlo simulations. The PSO algorithm is used for optimization of the AMS-SoC components using their metamodels instead of the actual circuit. The PSO algorithm followed a two step approach: local and global. The physical design of a Phase Locked Loop (PLL) is considered as a case study circuit. The proposed design flow is approximately 5 times faster while the error is under 2% compared to the Monte Carlo analysis.

Current Verilog-AMS system level modeling does not capture the physical design (layout) information of the target design as it is meant to be fast behavioral simulation only. Thus, the results of behavioral simulation can be very inaccurate. In this paper a paradigm shift of the current trend is presented that integrates layout level information (with full parasitics) in Verilog-AMS through polynomial metamodels such that system-level simulation of a mixed-signal circuit/system is realistic and as accurate as the true parasitic netlist simulation. As a specific case study, a voltage-controlled oscillator (VCO) Verilog-AMS behavioral model and design flow are proposed to assist fast PLL design exploration. Based on a quadratic polynomial metamodel, the PLL simulation achieves approximately a 10X speedup compared to the layout extracted, parasitic netlist. The simulations using this behavioral model attain high accuracy. The observed error for the simulated lock time and average power consumption are 0.7% and 3%, respectively. This behavioral metamodel approach bridges the gap between layout accurate but fast simulation and design space exploration.

This paper presents research leading to robust nano-CMOS sense amplifier design by incorporating process variation early in the design process. The effects of process variation are analyzed on the performance of a conventional voltage sense amplifier which is used in most DRAMs. A parametric study is performed through circuit simulations to investigate which parameters have the most impact on the performance of the sense amplifier. The Figures of Merit (FoMs) used to characterize the circuit are precharge time, power dissipation, sense delay and sense margin. Statistical analysis is performed to examine the impact of process variations on each FoM. By analyzing the results from the statistical study, a method is presented to select parameter values that minimize the effects of process variation. In this context, the well-established process-level techniques dual-threshold voltage and dual-oxide thickness are, for the first time, investigated for efficient sense amplifier design. Experimental results prove that the proposed approach improves precharge time by 63.3%, sense delay by 53.6%, sense margin by 39.3%, and power dissipation by 23.3% for 45 nm CMOS.

In this paper, we present the design of a P4 (Power-Performance-Process-Parasitic) aware voltage controlled oscillator (VCO) at nano-CMOS technologies. Through simulations, we have shown that parasitics and process have a drastic effect on the performance (center frequency) of the VCO. For process variation analysis, we propose a methodology called Design of Experiments-Monte Carlo (DOE-MC), which offers up to 6.25x time savings over a traditional Monte Carlo (TMC) method. A performance optimization of the VCO along with dual-oxide power minimization technique has been carried out in the presence of worst case process. The end product of the proposed methodology is a process aware, performance optimized, dual oxide VCO physical design. We have achieved 25% power (including leakage) minimization with only 1% degradation in center frequency compared to target frequency, in the presence of worst-case process and parasitics. The dual-oxide physical design of the VCO is carried out at 90nm. To the best of the authors' knowledge, this is the first research reporting a dual-oxide nano-CMOS VCO design simultaneously optimized for power (including leakage), performance, parasitics and process.

This paper proposes a novel flow for parasitic and process-variation aware design of radio-frequency integrated circuits (RFICs). A nano-CMOS current-starved voltage controlled oscillator (VCO) circuit has been designed using this flow as a case study. The oscillation frequency is considered as the objective optimization function with the area overhead as constraint. Extensive Monte Carlo simulations have been carried out on the parasitic extracted netlist of the VCO to study the effect of process variation on the oscillation frequency. In the design cycle, a performance degradation of 43.5% is observed when the parasitic extracted netlist is subjected to worst-case process variation. The proposed design flow could bring the oscillation frequency within 4.5% of the target, leading to convergence of the complete design in only one design iteration. To the best of the authors' knowledge, this paper presents the first work focussed on a current starved VCO in which the combined effect of parasitics and process variations has been considered.

This paper presents a process variation tolerant, SoC ready, 1 GS/s, 6 bit flash analog-to-digital converter (ADC) suitable for integration into nanoscale digital CMOS technologies. The physical design is carried out with a generic 90 nm Salicide 1.2 V/2.5 V 1 Poly 9 Metal process design kit using Design for Manufacturability (DFM) methodologies. Post-layout simulation results at nominal supply and threshold voltages are presented. The parasitic-extracted physical design of the ADC has been simulated for a supply voltage variation of 10%, and threshold voltage mismatch of 5%. The results show maximum variations of 10.5% and 5.7% in the INL and DNL respectively, with nominal INL = 0.344 LSB and nominal DNL = 0.459 LSB, at a supply voltage of 1.2 V. The ADC consumes a peak power of 5.794 mW and an average power of 3.875 mW. The comparators used in the ADC have been designed using the threshold inverting technique.

For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorithm for the gate leakage current reduction by simultaneous scheduling, allocation and binding during behavioral synthesis. Gate leakage current reduction is based on the use of functional units of different oxide thickness while simultaneously accounting for process variations. We present a cost function that minimizes leakage and area overhead. The algorithm minimizes the cost function for a given delay trade-off factor. It uses a pre-characterized cell library for tunneling current, delay and area, expressed as analytical functions of the gate oxide thickness T/sub ox/. We tested our approach using a number of behavioral level benchmark circuits characterized for a 45nm library by integrating our algorithm into a high-level synthesis system. We obtained an average gate leakage reduction of 76.88% with an average area overhead of 17.38% for different delay trade-off factors ranging from 1.0 to 1.4.

Gate leakage (direct tunneling current for sub-65 nm CMOS) can severely affect both the transient and steady state behaviors of CMOS circuits. In this paper we quantify the transient and steady-state gate leakage effects as capacitances and state independent (equiprobable) average values, respectively. These metrics are characterized for two universal logic gates, 2-input NAND and NOR, and their sensitivity to variations in process and design parameters is studied. The effective tunneling capacitance of a logic gate is defined as the maximum change in tunneling current with respect to the rate of change of input voltage. It is an unique and novel metric and to our knowledge proposed here for the first time with respect to a logic gate. This metric concisely encapsulates both qualitative as well as quantitative information about the swing in tunneling current during state transitions while simultaneously accounting for the transition rate and represents the capacitive load of the logic gate due to transience in tunneling.

In this paper, we propose a new metric called "effective tunneling capacitance" (Cefft) to quantify the transient swing in the gate leakage (gate oxide tunneling) current due to state transitions. Cefftwhich is defined as the change in tunneling current with respect to the rate of change of input voltage is a unique metric and to our knowledge proposed here for the first time. This metric concisely encapsulates information about the swing in tunneling current during state transitions while simultaneously accounting for the transition rate and represents the capacitive load of the transistor due to tunneling. This capacitance can have impact on transistor characteristics being additive to its gate oxide and diffusion capacitances. We express Cefftas functions of gate oxide thickness Toxand on-chip power supply VDDto make it useful for modeling in higher levels of design abstraction. We also statistically analyze the effects of process variations of Toxand VDDon its distribution

With aggressive technology scaling, gate oxide tunneling current is emerging as a prominent component of power dissipation in nanoCMOS circuits. This paper presents a novel approach for reduction of tunneling current (gate leakage) during behavioral synthesis using simultaneous scheduling and binding of resources made of transistors of different gate oxide thicknesses. We provide a heuristic algorithm for optimizing allocation and utilization of resources while scheduling operations with the objective of reducing gate leakage. We selectively bind the off-critical operations to instances of functional units that have transistors of higher oxide thickness, and critical operations to the functional units of lower oxide thickness. We performed extensive experiments for several behavioral synthesis benchmarks using a 45nm technology library. For a time constrained approach we achieved a maximum reduction of 84.8%, while for a resource-time constrained approach the reduction is 75.8%

In this paper we present a robust and novel strategic invisible approach for insertion-extraction of a digital watermark, a color image, into color images. The novelty of our scheme lies in determining a perceptually important sub-image in the host image so that slight tampering of the sub-image will affect the aesthetic of the host image significantly. This eliminates the possibility of watermark removal, which in turn makes the watermark secure and robust. The other novel feature of our algorithm is the creation of a compound watermark image, called effective watermark, using the input user watermark (logo) and attributes of host image, which facilitates robust insertion-extraction processes. The effective watermark creation consists of two distinct phases: in the first phase, a statistical image is synthesized from a perceptually important sub-image of the host image and in the second phase, a compound image is created by fusing the input logo and synthetic statistical image. Results of exhaustive experimentation using standard benchmarks demonstrates the robustness and efficacy of our approach

With continued and aggressive scaling, using ultra-low thickness SiO/sub 2/ for the transistor gates, tunneling current has emerged as the major component of leakage in CMOS circuits. In this paper, we propose a new approach called dual dielectrics of dual thicknesses (DKDT) for the reduction of both ON and OFF state gate tunneling currents. We claim that the simultaneous utilization of SiON and SiO/sub 2/ each with multiple thicknesses is a better approach for gate leakage reduction than the conventional one that uses a single gate dielectric, SiO/sub 2/, of multiple thicknesses. We develop an algorithm for the corresponding assignment of dual dielectric and dual thickness cells that minimizes the overall tunneling current for a circuit without compromising its performance. We performed extensive experiments on ISCAS'85 benchmarks using 45 nm technology which demonstrate that our approach can reduce the tunneling current by as much as 98.7% (on average 94.8%), without performance degradation.