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Minjae Kim 0010

dblp:16/418-10 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2025
0009-0009-7248-7923ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Memory systems · 72% Processor architecture and microarchitecture · 18% Cloud and datacenter computing · 9%
Software engineering, system software, and programming languages
1 paper
Operating systems · 100%

Topics — the 13 heaviest of 13, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › memory management › virtual memory
address translation
0.912025
HashScape: Leveraging Virtual Address Dynamics for Efficient Hashed Page Tables · IEEE Trans. Computers 2025
Memory systems › memory management › virtual memory › page table
hashed page tables
0.912025
HashScape: Leveraging Virtual Address Dynamics for Efficient Hashed Page Tables · IEEE Trans. Computers 2025
Memory systems › memory management › virtual memory
page table
0.912025
HashScape: Leveraging Virtual Address Dynamics for Efficient Hashed Page Tables · IEEE Trans. Computers 2025
Memory systems › memory management
virtual memory
0.912025
HashScape: Leveraging Virtual Address Dynamics for Efficient Hashed Page Tables · IEEE Trans. Computers 2025
Memory systems
cache
0.712023
McCore: A Holistic Management of High-Performance Heterogeneous Multicores · MICRO 2023
Memory systems › cache management
cache interference
0.712023
McCore: A Holistic Management of High-Performance Heterogeneous Multicores · MICRO 2023
Processor architecture and microarchitecture › multicore design
heterogeneous multicore
0.712023
McCore: A Holistic Management of High-Performance Heterogeneous Multicores · MICRO 2023
Processor architecture and microarchitecture
multicore design
0.712023
McCore: A Holistic Management of High-Performance Heterogeneous Multicores · MICRO 2023
Cloud and datacenter computing › resource management
shared resource management
0.712023
McCore: A Holistic Management of High-Performance Heterogeneous Multicores · MICRO 2023
Operating systems › resource management
memory management
0.312025
HashScape: Leveraging Virtual Address Dynamics for Efficient Hashed Page Tables · IEEE Trans. Computers 2025
Operating systems › resource management › memory management › virtual memory
page fault handling
0.312025
HashScape: Leveraging Virtual Address Dynamics for Efficient Hashed Page Tables · IEEE Trans. Computers 2025
Memory systems
memory bandwidth
0.212023
McCore: A Holistic Management of High-Performance Heterogeneous Multicores · MICRO 2023
Memory systems
memory bandwidth management
0.212023
McCore: A Holistic Management of High-Performance Heterogeneous Multicores · MICRO 2023

Methods — techniques the papers use, named apart from their topics

holistic resource management · 0.7
YearPublicationVenuePosition
2025 HashScape: Leveraging Virtual Address Dynamics for Efficient Hashed Page Tables
abstract
The evolving memory landscape for larger capacity prompts alternative approaches due to scalability challenges in multi-level page tables, which require multiple serial memory accesses for address translation. Hashed Page Tables (HPTs) have gained attention for ideally facilitating a single memory access per translation. However, current HPTs increase minor page fault latency, thereby impeding its superiority over conventional multi-level page table design. This paper provides a comprehensive analysis of HPTs regarding minor page fault latency concerning memory management subsystems. In particular, we demonstrate how feasibility issues in memory management with HPTs can escalate minor page fault latency. We observe that different page types in HPTs (anon pages and page caches) exhibit distinct behaviors on the occurrence of minor page faults, indicating a significant correlation between page types and minor page faults. To address these challenges, we proposeHashScape, a scheme that harmonizes with memory management using tailored HPTs per segment and size-tailored allocation via Virtual Memory Areas. Our evaluation demonstrates that HashScape significantly improves the insertion latency, with average, 95th, and 99thpercentiles improving by 1.8$\boldsymbol{\times}$, 1.9$\boldsymbol{\times}$, and 2.2$\boldsymbol{\times}$, respectively, resulting in an overall 10% reduction in minor page fault latency compared to a state-of-the-art HPT design.
Won Hur, Jiwon Lee 0001, Jaewon Kwon, Minjae Kim 0010, Won Woo Ro
IEEE Trans. Computers4
2023 McCore: A Holistic Management of High-Performance Heterogeneous Multicores
abstract
Heterogeneous multicore systems have emerged as a promising approach to scale performance in high-end desktops within limited power and die size constraints. Despite their advantages, these systems face three major challenges: memory bandwidth limitation, shared cache contention, and heterogeneity. Small cores in these systems tend to occupy a significant portion of shared LLC and memory bandwidth, despite their lower computational capabilities, leading to performance degradation of up to 18% in memory-intensive workloads. Therefore, it is crucial to address these challenges holistically, considering shared resources and core heterogeneity while managing shared cache and bandwidth.
Jaewon Kwon, Yongju Lee 0003, Hongju Kal, Minjae Kim 0010, Youngsok Kim, Won Woo Ro
MICRO4