Demo Data from VLDB 2026 / reviewers in the wild / expert
Erling Wold
dblp:16/420 · also Erling Henry Wold
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 1985
0009-0000-1336-192XORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-authorGraphics, computer vision, multimedia, augmented reality and games · 1Human-computer interaction and ubiquitous computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer graphics and multimedia
1 paper |
Rendering · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 61% Processor architecture and microarchitecture · 30% Integrated circuit design · 9% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Rendering
antialiasing |
0.0 | 1 | 1985 | Antialiasing through stochastic sampling · SIGGRAPH 1985 |
Rendering
ray tracing |
0.0 | 1 | 1985 | Antialiasing through stochastic sampling · SIGGRAPH 1985 |
Rendering › sampling
stochastic sampling |
0.0 | 1 | 1985 | Antialiasing through stochastic sampling · SIGGRAPH 1985 |
Hardware accelerators and domain-specific architectures › signal processing accelerator
FFT processor |
0.0 | 1 | 1984 | Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations · IEEE Trans. Computers 1984 |
Processor architecture and microarchitecture
pipelining |
0.0 | 1 | 1984 | Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations · IEEE Trans. Computers 1984 |
Hardware accelerators and domain-specific architectures
signal processing accelerator |
0.0 | 1 | 1984 | Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations · IEEE Trans. Computers 1984 |
Integrated circuit design
VLSI design |
0.0 | 1 | 1984 | Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations · IEEE Trans. Computers 1984 |
Methods — techniques the papers use, named apart from their topics
poisson sampling · 0.0parallel-pipeline architecture · 0.0filtered sampling · 0.0adaptive sampling · 0.0FFT algorithm · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1985 | Antialiasing through stochastic samplingabstractStochastic sampling techniques, in particular Poisson and fittered sampling, are developed and analyzed. These approaches allow the construction of alias-free approximations to continuous functions using discrete calculations. Stochastic sampling scatters high frequency information into broadband noise rather than generating the false patterne produced by regular sampling. The type of randomness used in the sampling process controls the spectral character of the noise. The average sampling rate and the function being sampled determine the amount of noise that is produced. Stochastic sampling is applied adaptively so that a greater number of samples are taken where the function varies most. An estimate is used to determine how many samples to take over a given region. Noise reducing filters are used to increase the efficacy of a given sampling rate. The filter width is adaptively controlled to further improve performance. Stochastic sampling can be applied spatiotemporally as well as to other aspects of scene simulation. Ray tracing is one example of an image synthesis approach that can be antialiased by stochastic sampling. Mark A. Z. Dippé, Erling Wold |
SIGGRAPH | 2 |
| 1985 | Fast fourier transform processors using Gaussian residue arithmetic
Alvin M. Despain, Allen M. Peterson, Oscar S. Rothaus, Erling Wold |
J. Parallel Distributed Comput. | 4 |
| 1984 | Pipeline and Parallel-Pipeline FFT Processors for VLSI ImplementationsabstractIn some signal processing applications, it is desirable to build very high performance fast Fourier transform (FFT) processors. To meet the performance requirements, these processors are typically highly pipelined. Until the advent of VLSI, it was not possible to build a single chip which could be used to construct pipeline FFT processors of a reasonable size. However, VLSI implementations have constraints which differ from those of discrete implementations, requiring another look at some of the typical FFT'algorithms in the light of these constraints. Erling Wold, Alvin M. Despain |
IEEE Trans. Computers | 1 |