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Ulrich Lauther

dblp:16/4643 · DBLP profile ↗
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15ranked-venue papers
9as first author
0since 2021 · last 2010
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 10 · 4 first-authorTheory of computation · 5 · 5 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
6 papers
Electronic design automation · 94% Integrated circuit design · 6%
Theoretical computer science
3 papers
Algorithms and data structures · 38% Computational geometry · 33% Graph algorithms and graph theory · 29%

Topics — the 13 heaviest of 14, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
design space exploration
0.011990
Global Hardware Synthesis from Behavioral Dataflow Descriptions · DAC 1990
Electronic design automation
high-level synthesis
0.011990
Global Hardware Synthesis from Behavioral Dataflow Descriptions · DAC 1990
Electronic design automation
physical design
0.031981
An O (N log N) algorithm for Boolean mask operations · DAC 1981
A data structure for gridless routing · DAC 1980
A min-cut placement algorithm for general cell assemblies based on a graph representation · DAC 1979
Electronic design automation › physical design › routing › detailed routing
gridless routing
0.011980
A data structure for gridless routing · DAC 1980
Electronic design automation › physical design
routing
0.011980
A data structure for gridless routing · DAC 1980
Electronic design automation › physical design › placement › partitioning-based placement
min-cut placement
0.011979
A min-cut placement algorithm for general cell assemblies based on a graph representation · DAC 1979
Electronic design automation › physical design
placement
0.011979
A min-cut placement algorithm for general cell assemblies based on a graph representation · DAC 1979
Electronic design automation
logic synthesis
0.011977
The siemens-avesta-system for computer-aided design of MOS-standard cell circuits · DAC 1977
Integrated circuit design › ASIC design
standard cell design
0.011977
The siemens-avesta-system for computer-aided design of MOS-standard cell circuits · DAC 1977
Computational geometry
spatial data structures
0.011980
A data structure for gridless routing · DAC 1980
Graph algorithms and graph theory
graph representation
0.011979
A min-cut placement algorithm for general cell assemblies based on a graph representation · DAC 1979
Integrated circuit design
digital circuit design
0.011977
The siemens-avesta-system for computer-aided design of MOS-standard cell circuits · DAC 1977
Integrated circuit design › digital circuit design
MOS circuits
0.011977
The siemens-avesta-system for computer-aided design of MOS-standard cell circuits · DAC 1977

Methods — techniques the papers use, named apart from their topics

bottom-up synthesis · 0.0
YearPublicationVenuePosition
2010 Space Efficient Algorithms for the Burrows-Wheeler Backtransformation
Ulrich Lauther, Tamás Lukovszki
Algorithmica1
2006 Multipole-Based Force Approximation Revisited - A Simple but Fast Implementation Using a Dynamized Enclosing-Circle-Enhanced k-d-Tree
Ulrich Lauther
GD1
2005 Space Efficient Algorithms for the Burrows-Wheeler Backtransformation
Ulrich Lauther, Tamás Lukovszki
ESA1
2001 Generating Schematic Cable Plans Using Springembedder Methods
Ulrich Lauther, Andreas Stübinger
GD1
1994 DA Algorithms in Non-EDA Applications: How Universal Are Our Techniques? (Panel)
abstract
No abstract available.
Patrick C. McGeer, Steven Trimberger, Erik Carlson, Dave Hightower, Ulrich Lauther, Alberto L. Sangiovanni-Vincentelli
DAC5
1990 Global Hardware Synthesis from Behavioral Dataflow Descriptions
abstract
This paper reports on a new bottom-up synthesis technique for general behavioral descriptions. Our technique extends traditional straight-line code synthesis by allowing hierarchical, block-structured dataflow graphs with block-level parallelism. Program path probabilities are taken into account; and both high-level synthesis and design-space exploration are addressed.
Josef Scheichenzuber, Werner Grass, Ulrich Lauther, Sabine März
DAC3
1990 Congestion-Driven Placement Using a New Multi-Partitioning Heuristic
abstract
A novel hierarchical top down placement technique is presented for circuits implemented in the sea-of-gates design style. It is based on a new hypergraph multi-partitioning algorithm, whose time complexity is linear in the number of pins of a circuit. The partitioning algorithm uses Steiner tress for the modeling of net topologies, which allows taking wiring congestion into account during placement. This leads to a more sophisticated balance criterion compared to conventional min-cut algorithms and consequently to a better distribution of active elements and wiring over the chip area. Experimental results show that the application of the new method makes the wiring of designs considerably easier.>
Stefan Mayrhofer, Ulrich Lauther
ICCAD2
1990 A New Global Router Based on a Flow Model and Linear Assignment
abstract
A novel heuristic for global routing in graphs is developed. Based on a flow model it can handle many nets simultaneously, thus reducing the net ordering problem. To demonstrate the validity of the method it was applied to standard cell design style. For this application the authors combined the flow model approach with linear assignment to achieve a hierarchical global routing scheme. This procedure is about six times faster than the old flat net by net global router, while producing denser layouts for the majority of testcases. Good quality was achieved in comparison with the TimberwolfSC version 5.4 global router.>
G. Meixner, Ulrich Lauther
ICCAD2
1983 HEX: An instruction-driven approach to feature extraction
Mark Hofmann, Ulrich Lauther
DAC2
1983 Gridless Channelrouting Revisited - a New Formulation of the Problem
Ulrich Lauther, Martin Nett
WG1
1981 An O (N log N) algorithm for Boolean mask operations
Ulrich Lauther
DAC1
1981 Additional Comments on " An Optimal Solution for the Channel-Assignment Problem"
abstract
The problem stated and solved in the above paper1has been solved before with essentially the same algorithm by Hashimoto and Stevens.
Ulrich Lauther
IEEE Trans. Computers1
1980 A data structure for gridless routing
abstract
A new data structure suitable for the implementation of gridless routing algorithms is presented. The data structure and some basic access procedures are outlined in PASCAL and experimental results are given to demonstrate the performance of retrieval algorithms working on the structure.
Ulrich Lauther
DAC1
1979 A min-cut placement algorithm for general cell assemblies based on a graph representation
Ulrich Lauther
DAC1
1977 The siemens-avesta-system for computer-aided design of MOS-standard cell circuits
Konrad W. Koller, Ulrich Lauther
DAC2