Frequency domain analysis of switched-capacitor and other clocked circuits including nonlinearities is a difficult problem requiring special attention. Conventional nonlinear frequency response methods are computationally intensive and time consuming for circuits with large transient components. In this paper, we present a novel technique for the rapid estimation of the nonlinear frequency response of switched-capacitor circuits. The analysis technique is formulated using a multifrequency sinusoidal excitation to drive the circuit into its steady-state condition. Then, the fundamental components are extracted using a frequency-directed Discrete Fourier Transform (DFT) in order to construct the frequency response. The key steps of this approach include the selection of noninterfering input frequencies and the determination of properly scaled input amplitudes. In addition, a method is proposed to reach steady-state quickly and to detect the steady-state condition for use in conjunction with the multifrequency approach described here.

Integrated circuit design has evolved to the stage where large, complex, analog and digital functionalities are implemented on a single chip or as an integrated chip set. Besides the mixed signal nature of the designs, the analog sections also include continuous-time and discrete-time components. Thus, for analysis of these integrated modules, all encompassing simulation capabilities are required that address, not only transient analysis of mixed analog-digital circuits, but frequency domain analysis as well. In this paper, we present mechanisms for multilevel and mixed-domain simulation of analog systems tied in with mixed analog-digital simulation. We then describe the implementation in the form of an open-ended and expandable simulation framework, iMACSIM. A simulation backplane is used to provide a general event-processing and scheduling framework that ties together the various algorithms necessary for simulation of various classes of circuits in different analysis regimes.

High-level design of analog systems is an open area that needs to be addressed with the emerging trend of integrating mixed analog-digital systems. Design methods compatible across the analog-digital boundaries would expedite the design process, and in this paper we address analog high-level design issues. An approach for systems-level synthesis of a class of analog systems is presented. A behavioral level for the analog domain is characterized in terms of state equations and transfer functions in the continuous and discrete domains. State-space representations are generated from transfer function specifications that exhibit system level characteristics such as controllability and observability as, well as decoupled and parallel architectures. These state-space representations are synthesized into behavioral-level, technology-independent architectures composed of analog functional components. An intermediate architecture in a circuit implementation technology is synthesized from the behavioral architecture. The various algorithmic procedures for synthesis are implemented in the program ARCHGEN. Behavioral simulation is used for architecture verification and design space exploration.>

Synthesis of analog circuits is an emergent field, with efforts focused at the cell level. With the growing trend of mixed ASIC designs that contain significant portions of analog sections, compatible design methodologies in the analog domain are necessary to complement those in the digital domain. The synthesis process requires an associated verification process to ensure that the designs meet performance specifications at the onset. In this paper we present a behavioral simulation methodology for analog system design verification and design space exploration. The verification task integrates with analog system-level synthesis for an integrated synthesis-verification process that avoids expensive post synthesis simulation by invoking external simulators. Thus rapid redesign at the architectural level can be undertaken for design parameter variation and during optimization. The verification suite is composed of a repertoire of analysis modes that include time and frequency domain analysis, sensitivity analysis and distortion analysis. Besides verification of design specifications, these analysis modes are also used to generate metrics for comparison of various architectural choices that could realize a given set of specifications. The implementation is in the form of a behavioral simulator, ARCHSIM.>

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