Traditional parallel event-driven HDL simulation methods suffer heavy synchronization & communication overhead for timely transferring the signal data among local simulators, which could easily nullify most of the expected simulation speed-up from parallelization. A new predictive parallel event-driven HDL simulation as a new promising approach had been proposed for enhancing simulation performance. In this paper, we have further enhanced this noble parallel simulation method for a series of not only timing, but also function oriented design changes with a new powerful prediction strategy. Experimentation with real SOC designs from industry has been performed for actual design changes, and shown the effectiveness of the enhanced approach.

Multilevel temporal-parallel event-driven simulation is a new radically different approach to simulation of designs described in Verilog HDL. It is based on a concept of time-parallel simulation applied to gate-level timing simulation. The simulation is performed in two steps: 1) fast reference simulation that runs on a higher, reference-level design model (typically RTL) and saves the design state at predetermined checkpoints; and 2) target simulation, which runs on a lower, gate-level model and distributes the simulation run slices to individual simulators. The paper addresses a number of important issues that make this approach practical: 1) finding initial state for each simulation slice; 2) resolving initial state mismatches; and 3) handling designs with multiple asynchronous clocks. Experimental results performed on industrial designs demonstrate the validity and efficiency of the method in terms of its performance and the debugging efficiency.

Simulation speedup offered by distributed parallel event-driven simulation is known to be seriously limited by the synchronization and communication overhead. These limiting factors are particularly severe in gate-level timing simulation. This paper describes a radically different approach to gate-level simulation based on a concept of temporal rather than conventional spatial parallelism. The proposed method partitions the entire simulation run into simulation slices in temporal domain and each slice is simulated separately. With each slice being independent from each other, an almost linear speedup is achievable with a large number of simulation nodes. This concept naturally enables “correct by simulation” methodology that explicitly maintains the consistency between the reference and the target specifications. Experimental results clearly show a significant simulation speed-up.

This paper describes a new and efficient solution to a distributed event-driven gate-level HDL simulation. It is based on a novel concept of spatial parallelism using accurate prediction of input and output signals of individual local modules in local simulations, derived from a model at a higher abstraction level (RTL). Using the predicted rather than actual signal values makes it possible to eliminate or greatly reduce the communication and synchronization overhead in a distributed event-driven simulation.

Simulation-based functional verification is characterized by two inherently conflicting targets: the signal visibility and simulation performance. Achieving a proper trade-off between these two targets is of paramount importance. Even though HDL simulators are the most widely used verification platform at the RTL and gate level, their major drawback is the low performance in verifying complex SOCs, especially when the high visibility over the design under verification is required. This paper presents a new, fast simulation method as an effective way to achieve both high simulation speed and full signal visibility. It is based on an original two-pass simulation approach. During the 1stpass, with the simulation running at full speed, a set of design states is saved periodically at predetermined checkpoints. During the 2ndpass, another simulation is performed, using any of saved checkpoints and providing 100% signal visibility for debugging. Our method differs from the traditional simulation snapshot approach in the amount and the way the design state is saved. Experimental results show significant speed-up compared to existing traditional simulation methods while maintaining 100% visibility.

In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The length and number of feedback cycles are reduced with minimal switching activity on the state variables. Experiment shows significant improvement in power dissipation and testabilities for benchmark circuits.

An efficient method for PLA decomposition, in which a single two-level Boolean function (PLA) is decomposed into two stages of cascaded PLAs such that the total area of all PLAs is smaller than that of the original PLA, is presented. The first stage may contain an arbitrary number of PLAs (generalized decoders), and the second stage contains a single PLA. Primary inputs are partitioned into disjoint sets of input variables and represented as multiple-valued variables so as to minimize the total PLA area. Two efficient algorithms for assignment of input variables to individual decoders are presented, one based on an integer programming technique and the other on graph partitioning. The constrained input encoding of the second-stage PLA is performed by an efficient procedure based on graph coloring and partitioning theory.>

A novel theoretical formulation of the input encoding problem is presented, based on the concept of compatibility of dichotomies. The input encoding problem is shown to be equivalent to a two-level logic minimization. Three possible techniques to solve the encoding problem are discussed, based on: techniques borrowed from classical logic minimization (generation of prime dichotomies and solving the covering problem); graph coloring applied to the graph of incompatibility of dichotomies; and extraction of essential prime dichotomies followed by graph coloring. The extraction of essential prime dichotomies serves the same purpose as the extraction of essential prime implicants in logic minimization, in the sense that it reduces the size of the covering/graph coloring problem. The conditions of optimality of the solutions to the input encoding problem are discussed. For near-optimum results a powerful heuristic, based on an iterative improvement technique, has been developed and implemented as a computer program: dichotomy-based symbolic input encoding technique (DIET). The test results indicate the DIET compares favorably with KISS and NOVA in terms of the CPU time, is superior to both programs in terms of the encoding length, and requires considerably less memory. This method can be applied to the input encoding of combinational logic and the state assignment of finite state machines (FSMs) in both two-level and multilevel implementations.>

A method for PLA (programmable logic array) decomposition is presented whereby a single two-level Boolean function (PLA) is decomposed into two levels of cascaded PLAs. Primary inputs are partitioned into disjoint sets and represented as multiple-valued variables so as to minimize the total PLA area. Two new algorithms are presented for input variable assignment, based on (a) graph partitioning and (b) a mathematical optimization method. The constrained output encoding of first-level PLAs is performed by a fast and efficient procedure based on a graph-coloring technique.>