Hyperspectral and multispectral imaging maintains a crucial role in remote sensing technology for Earth observation missions. However, the huge volume of produced data requires compression for storage and downlink transmission. In 2019, the Consultative Committee for Space Data Systems (CCSDS) released the CCSDS 123.0-B-2 recommended standard, allowing near-lossless compression, through a closed-loop quantizer, by introducing a Hybrid Entropy Coder option. However, the in-loop quantizer introduced additional data dependencies constituting a throughput performance bottleneck. This contribution addresses the need for high data-rate on-board compression by presenting an efficient parallel architecture and hardware implementation based on CCSDS 123.0-B-2. It bypasses the throughput performance bottleneck with an external, hardware-efficient quantizer while maintaining competitive quality near-lossless functionality with compatibility to the CCSDS standard. The parallel architecture leverages segmentation along the X-axis of the spectral cube, enabling scalable data-rate performance with constant embedded memory footprint. The introduced architecture is implemented in VHSIC hardware description language (VHDL) indicatively targeting Xilinx Kintex UltraScale technology, validated and demonstrated using state-of-the-art SpaceFibre serial link interface IP Cores and test equipment, achieving very high code coverage. A single hyperspectral compression engine (HCE) achieves throughput performance of 285 MSamples/s (4.56 Gb/s) at 1.68 W, while six parallel HCEs reach 1590 MSamples/s (25.44 Gb/s) at 6.12 W, measured on a full breadboard system. Maximum performance only depends on image dimensions, available field programmable gate array (FPGA) resources and high-speed serial interface technology. To the best of our knowledge, this implementation achieves the highest data-rate performance for near-lossless compression based on CCSDS 123.0-B-2 implemented in FPGA technology suitable for next-generation institutional missions.

Hyperspectral imaging is a key remote sensing technology. The explosive growth in hyperspectral image data volume (several TBs per orbit) and instrument data rates (in the range of 20 Gbps), compete with limited available on-board storage resources and downlink bandwidth, making hyperspectral image data compression a mission critical on-board data processing task. In order to provide continuous and reliable data transfer from the on-board systems to the ground stations, channel coding is being applied at the end of the data processing pipeline to guarantee reliable communications even at low signal-to-noise ratio regimes. Moreover, erasure correcting codes working on information packets rather than bits or symbols, can provide downlink reliability in future RF and optical links especially when Automatic Repeat Queuing (ARQ) strategies are either problematic or impossible due to specific service delay constraints and intermittent connectivity. Committed to the vision for "Space Technology Designed in Greece", in this special session paper, we provide an overview of cutting-edge technology high-performance hardware accelerators developed in the NKUA Digital Systems and Computer Architecture Laboratory (DSCAL), applicable to next-generation payloads for earth observation, optical/RF communication and connectivity, including CCSDS hyperspectral image compression and channel-coding at bit-level and packet-level.

Quasi-cyclic low-density parity-check (QC-LDPC) codes have been adopted by the Consultative Committee for Space Data Systems (CCSDS) as the recommended standard for onboard channel coding in Near-Earth and Deep-Space communications. Encoder architectures proposed so far are not efficient for high-throughput hardware implementations targeting the specific CCSDS codes. In this article, we introduce a novel architecture for the multiplication of a dense quasi-cyclic (QC) matrix with a bit vector, which is the fundamental operation of QC-LDPC encoding. The architecture leverages the inherent parallelism of the QC structure by concurrently processing multiple bits, according to an optimized scheduling. Based on this architecture, we propose efficient encoders for CCSDS codes, according to all the applicable low-density parity-check (LDPC) code encoding methods. Moreover, in the special case of the code for Near-Earth communications, we also introduce a preprocessing algorithm to efficiently handle the challenges arising from the generator's matrix circulant size (511 bits). The proposed architectures have been implemented in various field-programmable gate array (FPGA) technologies and validated in Zynq UltraScale+ multiprocessor system-on-chip (MPSoC), achieving a significant speedup compared with previous approaches, while at the same time keeping resource utilization low.

Nowadays, hyperspectral imaging is recognized as a cornerstone remote sensing technology. Next generation, high-speed airborne, and space-borne imagers have increased resolution, resulting in an explosive growth in data volume and instrument data rate in the range of gigapixel per second. This competes with limited on-board resources and bandwidth, making hyperspectral image compression a mission critical on-board processing task. At the same time, the “new space” trend is emerging, where launch costs decrease, and agile approaches are exploited building smallsats using commercial-off-the-shelf (COTS) parts. In this contribution, we introduce a high-performance parallel implementation of the CCSDS-123.0-B-1 hyperspectral compression algorithm targeting SRAM field-programmable gate array (FPGA) technology. The architecture exploits image segmentation to provide the robustness to data corruption and enables scalable throughput performance by leveraging segment-level parallelism. Furthermore, we exploit the capabilities of a COTS FPGA system-on-chip (SoC) device to optimize size, weight, power, and cost (SWaP-C). The architecture partitions a hyperspectral cube stored in a DRAM framebuffer into segments, compressing them in parallel using a flexible software scheduler hosted in the SoC CPU and several compressor accelerator cores in the FPGA fabric. A 5-core implementation demonstrated on a Zynq-7045 FPGA achieves a throughput performance of 1387 Msamples/s [22.2 Gb/s at 16 bits per pixel per band (bpppb)] and outperforms previous implementations in equivalent FPGA technology, allowing seamless integration with next-generation hyperspectral sensors.

Quasi-Cyclic Low-Density Parity-Check Codes (QC-LDPC) have been recently adopted by the Consultative Committee for Space Data Systems (CCSDS) as recommended standard for channel coding in near-earth (C2) and deep-space (AR4JA) communications. Existing QC-LDPC encoder architectures proposed in the literature so far, are optimized for other standards (e.g. DVB-S2, IEEE 802.11e), but they are not suitable for efficient implementations for the specific CCSDS codes. In this paper, we introduce for the first time a novel encoder architecture, suitable for these codes. The architecture is a parallel implementation based on a series of recursive convolutional encoders and it leverages the inherent parallelism of generator's matrix QC structure to boost throughput performance. Furthermore, the generic definition of key encoder's parameters provides increased flexibility in terms of latency, FPGA resources and speed. In the special case of C2 code for near-earth communications, a novel architecture is introduced to efficiently handle the challenges arising from the generator's matrix circulant size (511 bits), which is not a power of 2. The proposed encoders operate on a continuous uninterrupted stream of input data and implement all the functions specified by CCSDS data-link layer protocols (i.e. framing, synchronization and randomization). The efficiency of the introduced architecture is demonstrated on a Xilinx XUPV5 development board, achieving multi-Gbps throughput and a significant speed-up when compared with existing approaches.

The current state-of-the-art space-grade reconfigurable SRAM FPGAs provide unprecedented levels of integration and performance and advanced features previously available only to commercial developers such as dynamic partial reconfiguration. On-board payload data processing based on an adaptable SRAM FPGA based hardware platform offers unique advantages over both one-time programmable anti-fuse FPGAs and ASICs, enabling an adaptable instrument with significant savings in mass, power, cost, resources and flexibility. In this paper, for the first time, we integrate the instrument system supervisor processor along with dedicated, adaptable and high-performance on-board data processing functions in a single-chip, dependable and adaptable payload Data Processing Unit (DPU), based on the space-grade Xilinx Virtex-5QV FPGA. The introduced single-chip DPU supports self-configuration management without the requirement of an external configurator/scrubber. Furthermore, a system-level SEE mitigation strategy is proposed that employs EDAC, TMR and internal scrubbing to guarantee total immunity under extremely harsh radiation environments. The functionality of the proposed single-chip DPU is validated using a hardware demonstrator platform that hosts the commercial equivalent (XC5VFX130T) of the space-grade Xilinx Virtex-5QV FPGA.

The current state-of-the-art radiation tolerant or hardened reconfigurable SRAM-based FGPAs offer qualification for space applications, dynamic partial reconfiguration for in-flight adaptability, high density and performance. These FPGAs are very suitable for implementation of digital signal processing algorithms, providing the possibility for orders of magnitude increases in performance over processor-based implementations and thus are well suitable to establish dependable reconfigurable space systems. Alternatively, reconfigurable Complex Programmable Logic Devices (CPLDs) can be used as low-cost, low-power solutions for non-critical space applications. In this paper, challenges and new trends for dependable reconfigurable space systems are discussed and illustrated with 3 case studies.

In the era of terascale integration, the “reliability wall” and the “power wall” arise as barriers imposing significant challenges to the microprocessor industry. Nowadays, on-line testing is essential for modern microprocessors to detect latent defects that either escaped manufacturing testing or appear during system operation. Moreover, many-core scaling is now facing the “power wall”. More cores can now be placed on a chip than can be concurrently operating due to energy/power limitations. Software-Based Self-Test (SBST) is a flexible and low-cost solution for on-line March test application and defect detection in small memories, such as L1 caches, that lack Memory Built-In Self-Test (MBIST) hardware. In this paper, a power-aware optimization of the SBST methodology introduced in [10] is presented targeting Ll caches by analyzing the unique characteristics of March SBST routines and possible power optimizations without sacrificing March test quality. Experimental results using an architectural-level-power evaluation framework based on GEM5 and McPAT show that the exploitation of Direct Cache Access (DCA) instructions introduced in [10] along with the application of compiler-based power optimizations can achieve significant power savings up to 82.27% and energy savings up to 84,89% for the UltraSPARC Tl processor core. To the best of our knowledge, this is the first paper that addresses power-aware SBST for L1 caches in microprocessors.

Nowadays, on-line testing is essential for modern microprocessors to detect latent defects that either escape manufacturing testing or appear during system operation. Small memories, such as L1 caches and translation lookaside buffers (TLBs) are not usually equipped with memory built-in self-test (MBIST) hardware. Software-based self-test (SBST) is a flexible and low-cost solution for on-line March test application and error detection in such small memories. Although, L1 caches and TLBs are small components, their reliable operation is crucial for the system performance due to the large penalties caused when L1 cache or TLB misses occur. In this paper, an SBST program development methodology is proposed for on-line testing of small cache memories in microprocessors. To overcome testability challenges that are due to the “hidden” or implicit operation of such memories, the proposed SBST methodology exploits: 1) existing special purpose instructions that modern instruction set architectures implement to access these cache arrays for debug-diagnostic (DD) purposes, termed hereafter direct cache access instructions and 2) performance monitoring and trap handling mechanisms. Besides, the proposed SBST methodology combines features that are crucial for on-line testing: a) compact test validation; b) simplified coding style; c) low invasiveness of the test program; and d) small memory footprint. The methodology is comprehensively demonstrated on the instruction and data L1 cache arrays and the instruction and data TLB arrays of OpenSPARC T1. Experimental results show that the exploitation of such DD instructions has a significant improvement of test time (up to 86% for instruction L1 cache, up to 87% for the data L1 cache, up to 37% for D-TLB, and up to 91% for I-TLB) when compared to SBST solutions that do not utilize these types of instructions.

Multicore architectures are employed in the majority of computing domains (general-purpose microprocessors as well as specialized high-performance architectures such as network processors). Online error detection in such chips can employ effective techniques from single core microprocessors, however, effective test scheduling should be employed to minimize the overall chip test execution time which can significantly increase due to congestion on common hardware resources used by the cores. In this paper, we analyze the most important aspects of online error detection and scheduling in multiprocessor chips and evaluate test execution time in several different configurations of Intel's SCC architecture.

Start of the "Special session 4B: Elevator talks" section of the conference record.

The flexibility that allows the application of different March tests is a critical requirement for on-line testing of memory arrays. In a previous study, we have introduced a low-cost software-based self test (SBST) program development methodology for on-line periodic testing of L1 caches that utilizes direct cache access (DCA) instructions and exploits the native monitoring hardware available in modern architectures. In this brief, we discuss a multithreaded optimization of this SBST methodology that exploits the thread level parallelism of multithreaded multicore architectures in order to speed up March test execution by elaborating the low level multiple sub-bank cache organization. The effectiveness of the methodology and its multithreaded optimization is demonstrated on the L1 caches of OpenSPARC T1 processor. Our results showed a speedup of more than 1.7 when the multithreaded optimization is applied and an acceptable performance overhead (less than 11%), even in intensive periodic test scenarios.

For small memory arrays that usually lack Memory Built-In Self-Test (MBIST), such as Translation Lookaside Buffer (TLB) arrays, Software-Based Self-Test (SBST) can be a flexible and low-cost solution for on-line March test application. In this paper, an SBST program development methodology is proposed for on-line testing of data TLB (D-TLB), both for data (SRAM) and tag (CAM) memory arrays. The SBST methodology exploits existing special purpose instructions that modern ISAs implement to access the TLBs for debug-diagnostic purposes, termed hereafter Direct TLB Access (DTA) instructions, as well as, the trap handler mechanism.

Wireless Sensor Network (WSN) nodes are often deployed in harsh environments where the possibility of permanent and especially intermittent faults due to environmental hazards is significantly increased, while silicon aging effects are also exacerbated. Thus, online and in-field testing is necessary to guarantee correctness of operation. At the same time, online testing of processors integrated in WSN nodes has the requirement of minimum energy consumption, because these devices operate on battery, cannot be connected to any external power supply, and the battery duration determines the lifetime of the system. Software-Based Self-Test (SBST) has emerged as an effective strategy for online testing of processors integrated in nonsafety critical applications. However, the notion of dependability includes not only reliability but also availability. Thus, in order to encase both aspects we present a methodology for the optimization of SBST routines from the energy perspective. The refined methodology presented in this paper is able to be effectively applied in the case that the SBST routines are not initially available and need to be downloaded to the WSN nodes, as well as the case that the SBST routines are available in a flash memory. The methodology is extended to maximize the energy gains for WSN architectures offering clock gating or Dynamic Frequency Scaling features. Simulation results show that energy savings at processor level are up to 36.5 percent, which depending on the characteristics of the WSN system, can translate in several weeks of increased lifetime, especially if the routines need to be downloaded to the WSN node.

Weighted pseudorandom built-in self test (BIST) schemes have been utilized in order to drive down the number of vectors to achieve complete fault coverage in BIST applications. Weighted sets comprising three weights, namely 0, 1, and 0.5 have been successfully utilized so far for test pattern generation, since they result in both low testing time and low consumed power. In this paper an accumulator-based 3-weight test pattern generation scheme is presented; the proposed scheme generates set of patterns with weights 0, 0.5, and 1. Since accumulators are commonly found in current VLSI chips, this scheme can be efficiently utilized to drive down the hardware of BIST pattern generation, as well. Comparisons with previously presented schemes indicate that the proposed scheme compares favorably with respect to the required hardware.

Nowadays, on-line testing is essential for modern high-density microprocessors to detect either latent hardware defects or new defects appearing during lifetime both in logic and memory modules. For cache arrays, the flexibility to apply online different March tests is a critical requirement. For small memory arrays that may lack programmable Memory Built-In Self-Test (MBIST) circuitry, such as L1 cache arrays, Software-Based Self-Test (SBST) can be a flexible and low-cost solution for on-line March test application. In this paper, an SBST program development methodology is proposed for online periodic testing of L1 data and instruction cache, both for tag and data arrays. The proposed SBST methodology utilizes existing special purpose instructions that modern Instruction Set Architectures (ISAs) implement to access caches for debug-diagnostic and performance purposes, termed hereafter Direct Cache Access (DCA) instructions, as well as, performance monitoring mechanisms to overcome testability challenges. The methodology has been applied to 2 processor benchmarks, OpenRISC and LEON3 to demonstrate its high adaptability, and experimental comparison results against previous contributions show that the utilization of DCA instructions significantly improves test code size (83%) and test duration (72%) when applied to the same benchmark (LEON3).

Wireless Sensor Network (WSN) applications often need to be deployed in harsh environments, where the possibility of faults due to environmental hazards is significantly increased, while silicon aging and wearout effects are also exacerbated. For such applications, periodic on-line testing of the WSN nodes is an important step towards correctness of operation. However, on-line testing of processors integrated in WSN nodes has to address the additional challenge of minimum energy consumption, because these devices operate on battery, which usually cannot be replaced and in the absence of catastrophic failures determines the lifetime of the system. In this paper initially we derive analytically the optimal way for executing on-line periodic test with adjustable period, taking into account the degrading behavior of the system due to silicon aging effects but also the limited energy budget of WSN applications. The test is applied in the form of Software-Based Self-Test (SBST) routines, thus we proceed to the power optimized development of SBST routines targeting the transition delay fault model that is well suited for detecting timing violations due to silicon aging. Simulation results show that energy savings for the final SBST routine at processor level are up to 35.4% and the impact of test in the battery life of the system is negligible.

Software-Based Self-Test (SBST) has emerged as an effective method for on-line testing of processors integrated in non safety-critical systems. However, especially for multi-core processors, the notion of dependability encompasses not only high quality on-line tests with minimum performance overhead but also methods for preventing the generation of excessive power and heat that exacerbate silicon aging mechanisms and can cause long term reliability problems. In this paper, we initially extend the capabilities of a multiprocessor simulator in order to evaluate the overhead in the execution of the useful application load in terms of both performance and energy consumption. We utilize the derived power evaluation framework to assess the overhead of SBST implemented as a test thread in a multiprocessor environment. A range of typical processor configurations is considered. The application load consists of some representative SPEC benchmarks, and various scenarios for the execution of the test thread are studied (sporadic or continuous execution). Finally, we apply in a multiprocessor context an energy optimization methodology that was originally proposed to increase battery life for battery-powered devices. The methodology reduces significantly the energy and performance overhead without affecting the test coverage of the SBST routines.

Software-Based Self-Test (SBST) has emerged as an effective alternative for processor manufacturing and in-system testing. For small memory arrays that lack BIST circuitry such as cache tag arrays, SBST can be a flexible and low-cost solution for March test application and thus a viable supplement to hardware approaches. In this paper, a generic SBST program development methodology is proposed for periodic in-system (on-line) testing of L1 data and instruction cache memory tag arrays (both for direct mapped and set associative organization) based on contemporary March test algorithms. The proposed SBST methodology utilizes existing special performance instructions and performance monitoring mechanisms of modern processors to overcome cache tag testability challenges. Experimental results on OpenRISC 1200 processor core demonstrate that high test quality of contemporary March test algorithms is preserved while low-cost in-system testing in terms of test duration and test code size is achieved.

Pseudo-exhaustive pattern generators for built-in self-test (BIST) provide high fault coverage of detectable combinational faults with much fewer test vectors than exhaustive generation. In (n,k)-adjacent bit pseudo-exhaustive test sets, all 2kbinary combinations appear to all adjacentk-bit groups of inputs. With recursive pseudoexhaustive generation, all (n,k)-adjacent bit pseudoexhaustive tests are generated fork¿nand more than one modules can be pseudo-exhaustively tested in parallel. In order to detect sequential (e.g., stuck-open) faults that occur into current CMOS circuits, two-pattern tests are exercised. Also, delay testing, commonly used to assure correct circuit operation at clock speed requires two-pattern tests. In this paper a pseudoexhaustive two-pattern generator is presented, that recursively generates all two-pattern (n,k)-adjacent bit pseudoexhaustive tests for allk¿n. To the best of our knowledge, this is the first time in the open literature that the subject of recursive pseudoexhaustive two-pattern testing is being dealt with. A software-based implementation with no hardware overhead is also presented.

Major microprocessor vendors have integrated functional software-based self-testing in their manufacturing test flows during the last decade. Functional self-testing is performed by test programs that the processor executes at-speed from on-chip memory. Multiprocessors and multithreaded architectures are constantly becoming the typical general-purpose computing paradigm, and thus the various existing uniprocessor functional self-testing schemes must be adopted and adjusted to meet the testing requirements of complex multiprocessors. A major challenge in porting a functional self-testing approach from the uniprocessor to the multiprocessor case is to take advantage of the inherent execution parallelism offered by the multiple cores and the multiple threads in order to reduce test execution time. In this paper, we study the application of functional self-testing to chip multithreaded (CMT) processors. We propose a method that exploits thread-level parallelism (TLP) to speed up the execution of self-test routines in every physical core of a multiprocessor chip. The proposed method effectively splits the self-test routines into shorter ones, assigns the new routines to the hardware threads of the core and schedules their execution in order to minimize the core idle intervals due to cache misses or long latency operations and maximize the utilization of core computing resources. We demonstrate our method in the open-source CMT multiprocessor model, Sunpsilas OpenSPARC T1, which contains eight CPU cores, each one supporting four hardware threads. Our experimental results show a self-test execution speedup of more than three times compared to the single thread execution.

Input Vector Monitoring Concurrent Built-In Self Test schemes provide the capability to perform testing while the Circuit Under Test operates normally, by exploiting vectors that appear at the inputs of the CUT during its normal operation. The Concurrent Test Latency of an input vector monitoring scheme is the time required for the concurrent test to complete. Input Vector Monitoring Concurrent BIST schemes that have been proposed to date, are based mainly on test sets containing binary (1 or 0) values. Test sets extracted by modern CAD tools, largely contain don't care (dasiaXpsila) values. In this work a novel input vector monitoring concurrent BIST scheme is presented, based on a test set containing dasiaXpsila values. The proposed scheme compares favourably with respect to the hardware overhead - concurrent test latency trade off with previously proposed techniques.

Software-based or instruction-based self-testing has recently emerged as an effective alternative for the manufacturing and online testing of microprocessors, and is progressively adopted by major microprocessor manufacturers mainly as a supplement to other mature and well-established testing approaches to reach higher test quality. Thus far, software-based self-test approaches presented in the literature have focused almost exclusively on uniprocessors. With the continuing prevalence of multiprocessors, the focus of such research approaches moves from the uniprocessor to the multiprocessor case. In this paper, we study the application of software-based self-testing on symmetric shared-memory multiprocessors (SMP) considering the most common interconnection architectures, shared bus and crossbar switch. We focus on the impact of the shared-memory system architecture, the cache coherence mechanisms, and the interconnection architecture on the execution time of self-test programs running on each separate core and exploit the SMP's parallelism during testing to reduce the test execution time. We propose a generic methodology that allocates the test programs and test responses into the shared on-chip memory and schedules the test routines among the cores aiming at the reduction of the total test application time, and thus, test cost, for the SMP, by increasing the execution parallelism and reducing both bus contentions and data cache invalidations. We demonstrate the proposed solutions with detailed experiments on several two-core, four-core, and eight-core SMP benchmarks based on a popular RISC benchmark processor using both the shared bus and the crossbar switch interconnection architectures.

Online periodic testing of microprocessors is a valuable means to increase the reliability of a low-cost system, when neither hardware nor time redundant protection schemes can be applied. This is particularly valid for floating-point (FP) units, which are becoming more common in embedded systems and are usually protected from operational faults through costly hardware redundant approaches. In this paper, we present scalable instruction-based self-test program development for both single and double precision FP units considering different instruction sets (MIPS, PowerPC, and Alpha), different microprocessor architectures (32/64-bit architectures) and different memory configurations. Moreover, we introduce bit-level manipulation instruction sequences that are essential for the development of FP unit's self-test programs. We developed self-test programs for single and double precision FP units on 32-bit and 64-bit microprocessor architectures and evaluated them with respect to the requirements of low-cost online periodic self-testing: fault coverage, memory footprint, execution time, and power consumption, assuming different memory hierarchy configurations. Our comprehensive experimental evaluations reveal that the instruction set architecture plays a significant role in the development of self-test programs. Additionally, we suggest the most suitable self-test program development approach when memory footprint or low power consumption is of paramount importance.

Functional, instruction-based self-testing of microprocessors has emerged as an effective alternative or supplement to other testing approaches, and is progressively adopted by major microprocessor manufacturers. In this paper, we study, for first time, the applicability of functional self-testing on bus-based symmetric multiprocessors (SMP) and the exploitation of SMPs parallelism during testing. We focus on the impact of the memory system architecture and the cache coherency mechanisms on the execution of self-test programs on the processor cores. We propose a generic self-test routines scheduling algorithm aiming at the reduction of the total test application time for the SMP by reducing both bus contention and data cache coherency invalidation. We demonstrate the proposed solutions with detailed experiments in two-core and four-core SMP benchmarks based on a RISC processor core.

Software-based self-test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical applications. Among the various systems that fall in the previous category, wireless sensor networks (WSN) are often deployed in harsh environments where the possibility of permanent and especially intermittent faults due to environmental hazards is significantly increased, thus on-line and in-field testing is necessary to guarantee the accuracy of the sensed values. At the same time, on-line testing of processors integrated in WSN has the extra requirement of minimum energy consumption, because these devices are operating on battery, cannot be connected to any external power supply, and the battery duration determines the lifetime of the system. In this paper we present a methodology for the optimization of SBST routines from the energy perspective. Techniques utilized for achieving energy reduction include energy aware loop synthesis, loop transformations, instruction substitution and register renaming. Simulation results show that the energy savings at processor level are up to 35.6%.

Built-In Self-Test (BIST) techniques constitute an effective and practical approach for VLSI circuits testing. BIST schemes are typically classified into two categories: off-line and on-line. Input vector monitoring concurrent BIST schemes are a class of on-line techniques that circumvent the problems appearing separately in on-line and in off-line BIST. The utilization of input vector monitoring concurrent BIST techniques provides the capability to perform testing at different stages, manufacturing, periodic off-line and concurrent online. The input vector monitoring concurrent BIST schemes proposed so far have targeted either exhaustive or pseudorandom testing separately. In this paper a novel input vector monitoring concurrent BIST scheme based on a pre-computed test set is presented. The proposed scheme can perform both concurrent on-line and off-line testing; therefore it can be equally well utilized for manufacturing and concurrent on-line testing in the field. The applicability of the scheme is validated with respect to the hardware overhead and the time required for completion of the test in benchmark circuits. To the best of our knowledge, the proposed scheme is the first to be presented in the open literature based on a pre-computed test set that can perform both concurrent on line and off-line testing.

Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving test related functions from external resources to the SoC's interior, in the form of test programs that the on-chip processor executes, SBST significantly reduces the need for high-cost, big-iron testers, and enables high-quality at-speed testing and performance binning. Thus far, SBST approaches have focused almost exclusively on the functional (programmer visible) components of the processor. In this paper, we analyze the challenges involved in testing an important component of modern processors, namely, the pipelining logic, and propose a systematic SBST methodology to address them. We first demonstrate that SBST programs that only target the functional components of the processor are not sufficient to test the pipeline logic, resulting in a significant loss of overall processor fault coverage. We further identify the testability hotspots in the pipeline logic using two fully pipelined reduced instruction set computer (RISC) processor benchmarks. Finally, we develop a systematic SBST methodology that enhances existing SBST programs so that they comprehensively test the pipeline logic. The proposed methodology is complementary to previous SBST techniques that target functional components (their results can form the input to our methodology, and thus we can reuse the test development effort behind preexisting SBST programs). We automate our methodology and incorporate it in an integrated software environment (developed using Java, XML, and archC) for the automatic generation of SBST routines for microprocessors. We apply the methodology to the two complex benchmark RISC processors with respect to two fault models: stuck-at fault model and transition delay fault model. Simulation results show that our methodology provides significant improvements for the two fault models, both for the entire processor (12% fault coverage improvement on average) and for the pipeline logic itself (19% fault coverage improvement on average), compared to a conventional SBST approach.

Software-based self-test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical embedded system applications. Among the most popular applications falling in this category are the various mobile devices. However, in-field testing of processors integrated in mobile devices has the extra requirement of minimum energy consumption, since these devices are operating on battery. In this paper initially we present the parameters contributing to energy consumption in order to set the scope of the problem and make a qualitative analysis about the efficiency of the SBST routines from a low energy perspective. Then we propose a power evaluation framework based on a combination of tools from the testing and computer architecture technical areas. Utilizing this framework we evaluate for the first time the most effective structural SBST strategies in terms of energy consumption for three representative processor configurations, showing the validity of our analysis. Finally, the SBST strategies are combined and an appropriate strategy for each processor component is selected, in order to minimize overall energy consumption during on-line testing up to an order of magnitude between the best and worst case combination of test routines.

Functional Software-Based Self-Testing (SBST) of microprocessors and processor-based testing of Systems-on- Chip (SoCs) have recently attracted the attention of test technology research community because they provide an effective alternative to other traditional testing and self- testing approaches. SBST allows at-speed functional testing of SoC cores with virtually no circuit overhead and limited dependence on external testers. Despite the importance of peripheral control cores in SoCs (in terms of functionality and size), the applicability and limits of SBST on them have not been comprehensively studied. In this paper, we study the effectiveness of SBST on a broad class of communication peripherals. A systematic application of SBST on two popular peripheral cores (UART and Ethernet) demonstrates the effectiveness of SBST on SoCs with such cores.

Speculative execution of instructions boosts performance in modern microprocessors. Control and data flow dependencies are overcome through speculation mechanisms, such as branch prediction or data value prediction. Because of their inherent self-correcting nature, the presence of defects in speculative execution units does not affect their functionality (and escapes traditional functional testing approaches) but impose severe performance degradation. In this paper, we investigate the effects of performance faults in speculative execution units and propose a generic, software-based test methodology, which utilizes available processor resources: hardware performance monitors and processor exceptions, to detect these faults in a systematic way. We demonstrate the methodology on a publicly available fully pipelined RISC processor that has been enhanced with the most common speculative execution unit, the branch prediction unit. Two popular schemes of predictors built around a Branch Target Buffer have been studied and experimental results show significant improvements on both cases fault coverage of the branch prediction units increased from 80% to 97%. Detailed experiments for the application of a functional self-testing methodology on a complete RISC processor incorporating both a full pipeline structure and a branch prediction unit have not been previously given in the literature.

Software-based self-testing (SBST) of microprocessors and processor-based testing of systems-on-chip (SoCs) recently captured intense test technology research efforts because they provide an effective alternative or supplement to other classic testing and self-testing approaches. Despite the importance of peripheral cores in SoCs (in terms of functionality and size), the applicability and limits of SBST on them have not been comprehensively studied. In this paper, we study the effectiveness of SBST on a broad class of communication peripheral cores in SoCs. A systematic application of SBST on two popular peripherals (universal asynchronous receiver transmitter and Ethernet) demonstrates the effectiveness of SBST on SoCs with such cores.

Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in Systems-on-Chip (SoCs). By moving test related functions from external resources to the SoC’s interior, in the form of test programs that the on-chip processor executes, SBST eliminates the need for high-cost testers, and enables high-quality at-speed testing. Thus far, SBST approaches have focused almost exclusively on the functional (directly programmer visible) components of the processor. In this paper, we analyze the challenges involved in testing an important component of modern processors, namely, the pipelining logic, and propose a systematic SBST methodology to address them. We first demonstrate that SBST programs that only target the functional components of the processor are insufficient to test the pipeline logic, resulting in a significant loss of fault coverage. We further identify the testability hotspots in the pipeline logic. Finally, we develop a systematic SBST methodology that enhances existing SBST programs to comprehensively test the pipeline logic. The proposed methodology is complementary to previous SBST techniques that target functional components (their results can form the input to our methodology), and can reuse the test development effort behind existing SBST programs. We applied the methodology to two complex, fully pipelined processors. Results show that our methodology provides fault coverage improvements of up to 15% (12 % on average) for the entire processor, and fault coverage improvements of 22 % for the pipeline logic, compared to a conventional SBST approach.

Today's nanometer technology trends have a very negative impact on the reliability of semiconductor products. Intermittent faults constitute the largest part of reliability failures that are manifested in the field during the semiconductor product operation. Since software-based self-test (SBST) has been proposed as an effective strategy for on-line testing of processors integrated in non-safety critical low-cost embedded system applications, optimal test period specification is becoming increasingly challenging. In this paper we first introduce a reliability analysis for optimal periodic testing of intermittent faults that minimizes the test cost incurred based on a two-state Markov model for the probabilistic modeling of intermittent faults. Then, we present for the first time an enhanced SBST strategy for on-line testing of complex pipelined embedded processors. Finally, we demonstrate the effectiveness of the proposed optimal periodic SBST strategy by applying it to a fully-pipelined RISC embedded processor and providing experimental results

In this paper, we introduce a fully automated low cost hardware/software platform for efficiently performing fault emulation experiments targeting SEUs in the configuration bits of FPGA devices, without the need for expensive radiation experiments. We propose a method for significantly reducing the fault list by removing the faults on unused LUT bit positions. We also target the design flip-flops found in the configurable logic blocks (CLBs) inside the FPGA. Run-time reconfigurability of Virtex devices using JBits is exploited to provide the means not only for fault injection but fault detection as well. First, we consider five possible application scenarios for evaluating different self-test schemes. Then, we apply the least favorite and most time consuming of these scenarios on two 32times32 multiplier designs, demonstrating that transferring the simulation processing workload to FPGA hardware can allow for acceleration of simulation time of more than two orders of magnitude

High-speed datapaths in microprocessors and embedded processors contain complex floating-point (FP) arithmetic units which have a critical role in the processor's performance. Although the FP units' complex structure consists of classic integer arithmetic components, the embedded components encounter serious testability problems due to their limited accessibility from the FP unit ports and testability loss due to FP unit inherent operations, such as rounding and normalization. In this paper, we analyze the testability problems and present scalable test generation for FP units using as a demonstration vehicle the popular, high-speed, two-path architecture of the most complex unit, the FP adder. The key feature of the presented methodology is the identification of testability conditions that guarantee effective test pattern application and fault propagation for each of the components of the FP adder. The identified test conditions can be utilized with respect to any fault model and are independent of the internal structure and the size of the components. Thus, they can be applied to FP adders of various exponent and significant sizes (single, double, and custom precision), as well as to other types of FP units, which also consist of classic integer arithmetic components similarly interconnected

Weighted pseudorandom BIST schemes have been efficiently utilized in order to drive down the number of vectors required to achieve complete fault coverage in built in self test (BIST) applications. Sets of patterns comprising weights 0, 0.5 and 1 have been successfully utilized within the weighted pattern generation paradigm. In this paper an accumulator-based scheme is presented, that generates set of patterns with weights 0, 0.5 and 1. Since accumulators and ALUs are commonly found in current VLSI chips, the presented scheme can be efficiently utilized to drive down the hardware of BIST pattern generation.

High performance real number operations in embedded processors' and microprocessors' datapaths are realized by floating point (FP) arithmetic units. FP units have a complex structure which although consisting of classic integer arithmetic components faces serious testability problems due to the limited accessibility of the components from the FP unit ports. In this paper we present a test generation methodology for FP adders based on the high-speed, two-path architecture. The key feature of the presented methodology is the identification of testability conditions that guarantee effective test pattern application and fault propagation for each of the components of the FP adder. According to our test methodology, the testability conditions guide test generation process. The identified test conditions are independent of the internal structure and the size of the components. Thus, they can be applied to floating point adders of various exponent and significand sizes built with components of different architectures.

Manufacturing testing is carried-out once in order to ensure the correct operation of the circuit under test right after fabrication, while either periodic off-line testing or concurrent on-line testing is carried-out in order to ensure that the circuit under test continues to operate correctly in field. The utilization of input vector monitoring concurrent BIST techniques provides the capability to perform all types of testing, namely manufacturing, periodic off-line and concurrent on-line. The input vector monitoring concurrent BIST schemes proposed so far have targeted either exhaustive or pseudorandom testing. In this paper a novel input-vector monitoring concurrent BIST scheme based on a pre-computed test set is introduced. To the best of our knowledge, the proposed scheme is the first to be presented in the open literature based on a pre-computed test set that can perform both on line and off-line testing

Embedded processor testing techniques based on the execution of self-test programs have been recently proposed as an effective alternative to classic external tester-based testing and pure hardware built-in self-test (BIST) approaches. Software-based self-testing is a nonintrusive testing approach and provides at-speed testing capability without any hardware or-performance overheads. In this paper, we first present a high-level, functional component-oriented, software-based self-testing methodology for embedded processors. The proposed methodology aims at high structural fault coverage with low test development and test application cost. Then, we validate the effectiveness of the proposed methodology as a low-cost alternative over structural software-based self-testing methodologies based on automatic test pattern generation and pseudorandom testing. Finally, we demonstrate the effectiveness and efficiency of the proposed methodology by completely applying it on two different processor implementations of a popular RISC instruction set architecture including several gate-level implementations.

Software-based self-test (SBST) strategies are particularly useful for periodic testing of deeply embedded processors in low-cost embedded systems with respect to permanent and intermittent operational faults. Such strategies are well suited to embedded systems that do not require immediate detection of errors and cannot afford the well-known hardware, information, software, or time-redundancy mechanisms. We first identify the stringent characteristics of a SBST program to be suitable for on-line periodic testing. Also, we study the probability for a SBST program to detect permanent and intermittent faults during on-line periodic testing. Then, we introduce a new SBST methodology with a new classification and test-priority scheme for processor components. After that, we analyze the self-test routine code styles for the three more effective test pattern generation (TPG) strategies in order to select the most effective self-test routine for on-line periodic testing of a component under test. Finally, we demonstrate the effectiveness of the proposed SBST methodology for on-line periodic testing by presenting experimental results for two pipeline reduced instruction set computers reduced instruction set processors of different architecture.

Microprocessor datapath architectures operate on signed numbers usually represented in two's-complement or sign-magnitude formats. The multiplication operation is performed by optimized array multipliers of various architectures which are often produced by automatic module generators. Array multipliers have either a standard, nonrecoded signed (or unsigned) architecture or a recoded (modified Booth's algorithm) architecture. High-quality testing of array multipliers based on a comprehensive sequential fault model and not affecting their well-optimized structure has not been proposed in the past. In this paper, we present a built-in self-testing (BIST) architecture for signed and unsigned array multipliers with respect to a comprehensive sequential fault model. The BIST architecture does not alter the well-optimized multiplier structure. The proposed test sets can be applied externally but their regular nature makes them very suitable for embedded, self-test application by simple specialized hardware which imposes small overheads. Two different implementations of the BIST architecture are proposed. The first implementation focuses on the test invalidation problem and targets robust sequential fault testing, while the second one focuses on test cost reduction (test time and hardware overhead).

Manufacturing test is carried-out once to ensure the correct operation of the circuit under test right after fabrication, while testing is carried-out periodically to ensure that the circuit under test continues to operate correctly on the field. The use of offline built-in self-test (BIST) techniques for periodic testing imposes the interruption of the normal operation of the circuit under test. On the other hand, the use of input vector monitoring concurrent BIST techniques for periodic testing provides the capability to perform the test, while the circuit under test continues to operate normally. In this paper, a novel input-vector monitoring concurrent BIST technique for combinational circuits based on a self-testing RAM, termed R-CBIST, is presented. The presented technique compares favorably to the other input vector monitoring concurrent BIST techniques proposed so far with respect to the hardware overhead, and the time required for the concurrent test to be completed (concurrent test latency). R-CBIST can be utilized to test ROM because it results in small hardware overhead, whereas there is no need to stop the ROM normal operation.

The detection of robustly detectable sequential faults has been extensively studied. A number of researchers have provided theoretical as well as experimental results designating that the application of single input change (SIC) pairs of test patterns results in favorable results for sequential fault testing. In this paper, a novel algorithm for the generation of SIC pairs is presented, termed Accumulator-based test generation for Robust sequential fault testing in Near-optimal time (ARN). ARN is implemented in hardware utilizing an accumulator whose inputs are driven by a barrel shifter. Since such structures are commonly found in general-purpose or specialized microprocessors or digital signal processors (DSP), the presented architecture provides a practical solution for the built-in testing of such circuits.

Software-based self-test (SBST) strategies are particularly useful for periodic testing of deeply embedded processors in low-cost embedded systems that do not require immediate detection of errors and cannot afford the well-known hardware, software, or time redundancy mechanisms. In this paper, first, we identify the stringent characteristics of an SBST test program to be suitable for on-line periodic testing. Then, we introduce a new SBST methodology with a new classification scheme for processor components. After that, we analyze the self-test routine code styles for the three more effective test pattern generation (TPG) strategies in order to select the most effective self-test routine for on-line periodic testing of a component under test. Finally, we demonstrate the effectiveness of the proposed SBST methodology for on-line periodic testing by presenting experimental results for a RISC pipeline processor.

A comprehensive online test strategy requires both concurrent and non-concurrent fault detection capabilities to guarantee SoCs's successful normal operation in-field at any level of its life cycle. While concurrent fault detection is mainly achieved by hardware or software redundancy, like duplication, non-concurrent fault detection, particularly useful for periodic testing, is usually achieved through hardware BIST. Software-based self-test has been recently proposed as an effective alternative to hardware-based self-test allowing at-speed testing while eliminating area, performance and power consumption overheads. In this paper we focus on the applicability of software-based self-test to non-concurrent on-line testing of embedded processor cores. Low-cost in-field testing requirements, particularly small test execution time and low power consumption guide the development of self-test routines. We show how self-test programs with a limited number of memory references and based on compact test routines provide an efficient low-cost on-line test strategy.

Embedded processor testing techniques based on the execution of self-test routines, have been recently proposed as an effective alternative to classical hardware Built-In Self Test. Software-based self-testing provides atspeed testing capability and does not add hardware or performance penalties. It efficiently partitions the testing task between external testers and internal processor resources. In this paper we analyze the application of a softwarebased self-testing methodology to different implementations of a complex embedded processor architecture. We demonstrate that such a methodology provides high test quality in different processor implementations with low test development and low test application costs. 1

Software self-testing for embedded processor cores based on their instruction set, is a topic of increasing interest since it provides an excellent test resource partitioning technique for sharing the testing task of complex systems-on-chip (SoC) between slow, inexpensive testers and embedded code stored in memory cores of the SoC. We introduce an efficient methodology for processor cores self-testing which requires knowledge of their instruction set and Register Transfer (RI) level description. Compared with functional testing methodologies proposed in the past, our methodology is more efficient in terms of fault coverage, test code size and test application time. Compared with recent software based structural testing methodologies for processor cores, our methodology is superior in terms of test development effort and has significantly smaller code size and memory requirements, while virtually the same fault coverage is achieved with an order of magnitude smaller test application time.

Instruction-based self-testing of embedded processor cores provides an excellent technique for balancing the testing effort for complex Systems-on-Chip (SoC) between slow, inexpensive external testers and embedded code stored in memory cores. In this paper we apply our efficient methodology for processor core self-testing based on the knowledge of its instruction set architecture and register transfer level description on a common accumulator-based processor core benchmark We also demonstrate that our methodology is superior in terms of test development effort and has significantly smaller code size and memory requirements, while the same fault coverage is achieved with an order of magnitude smaller test application time compared with a recently published structural methodology for processor core self-testing.

A deterministic software-based self-testing methodology for processor cores is introduced that efficiently tests the processor datapath modules without any modification of the processor structure. It provides a guaranteed high fault coverage without repetitive fault simulation experiments which is necessary in pseudorandom software-based processor self-testing approaches. Test generation and output analysis are performed by utilizing the processor functional modules like accumulators (arithmetic part of ALU) and shifters (if they exist) through processor instructions. No extra hardware is required and there is no performance degradation.

The modified Booth array multiplier is the most ubiquitous multiplier architecture in the datapaths of either general purpose microprocessors or specialized Digital Signal Processors. Sequential fault testing for Booth array multipliers has never been proposed in the past. In this paper, we present two BIST architectures for modified Booth array multipliers with respect to the Realistic Sequential Cell Fault model (RS-CFM). The first BIST architecture aims to resolve the test invalidation problem to the largest possible extent, while the second one aims to test cost reduction. Both BIST architectures achieve very high sequential fault coverage and impose moderate hardware and delay overhead. Simplified variations of the two BIST architectures are also presented for the non-recoded signed array multipliers. Thus, the proposed BIST architectures offer a universal BIST solution that covers the totality of signed array multipliers: non-recoded and recoded.

Power in processing cores (microprocessors, DSPs) is primarily consumed in the datapath part. Among the datapath functional modules, multipliers consume the largest amount of power due to their size and complexity. We propose a low power BIST scheme for datapaths built around multiplier-accumulator pairs. The target is low average power dissipation between successive test vectors. This is achieved by taking advantage of the regularity of multiplier modules and achieving very high fault coverage by a linear-sized test set with as small as possible input switching activity. The proposed BIST scheme is more efficient than pseudorandom BIST for the same high fault coverage target. Up to 77.2% power saving is achieved in the set of experimental results provided in the paper.

Power in processing cores (microprocessors, DSPs) is primarily consumed in the functional modules of the datapath. Among these modules, multipliers consume the largest amount of power due to their size and complexity. We propose low power BIST schemes for datapath architectures built around multiplier-accumulator pairs, based on deterministic test patterns. Two alternatives are proposed depending on whether the target is low energy dissipation during a BIST session or low power dissipation (i.e. average energy dissipation between successive test vectors). The proposed BIST schemes are more efficient than pseudorandom BIST for the same high fault coverage target. Up to 78.33% energy saving is achieved by the proposed low energy BIST scheme and up to 82.22% power saving is achieved by the proposed low power BIST scheme, compared with pseudorandom BIST.

Iterative Logic Arrays (ILAs) are widely used in the datapath parts of digital circuits, like general purpose microprocessors, embedded processors, and digital signal processors. Testing strategies based on more comprehensive fault models than the traditional combinational fault models have become an imperative need in CMOS technology. In this paper, first, we introduce a comprehensive, cell-level, sequential fault model suitable for ILAs, termed Realistic Sequential Cell Fault Model (RS-CFM). RS-CFM drastically reduces test complexity compared to exhaustive two-pattern testing proposed so far in the literature for sequential ILA testing, without sacrificing test quality. In addition, it favors robustness of sequential test sets both at the cell and the array levels. Second, a new Automatic Test Pattern Generator (ILA-ATPG) based on RS-CFM for the case of one-dimensional ILAs is presented. ILA-ATPG can handle all classes of one-dimensional ILAs: unilateral or bilateral ILAs, with or without vertical inputs/outputs. Based on a graph model, ILA-ATPG explores the C-testability and linear-testability of the ILA under test and resolves the test invalidation problem constructing robust test sequences. The efficiency of ILA-ATPG is demonstrated through a comprehensive set of experimental results over all classes of one-dimensional ILAs, including all practical one-dimensional ILAs, as well as a number of more complex benchmarks.

Wallace free summation in conjunction with Booth encoding are well known techniques to design fast multiplier cores widely used as embedded cores in the design of complex systems on chip. Testing of such multiplier cores deeply embedded in complex ICs requires the utilization of a BIST architecture that can be easily synthesized along with the multiplier by the module generator. In this paper we introduce an effective BIST architecture for fast multipliers that completely complies with this requirement. The algorithmic BIST patterns that this architecture generates guarantee a fault coverage higher than 99%. The required test pattern generator consists of a simple fixed-size binary counter, independent of the multiplier size. Accumulator-based compaction is adopted since multipliers and adders co-exist in most datapath architectures.

Sequential fault testing approaches for array multipliers proposed in the past target only external testing and impose significant hardware overhead due to excessive DFT modifications. In this paper we present, for the first time, a BIST architecture which does not require any DFT modifications in the multiplier structure and provides a fault coverage larger than 99% for a comprehensive sequential fault model (RS-CFM) for any multiplier size. Both robust and non-robust testing are considered. The applicability of the BIST architecture is further justified considering the case of the transistor stuck-open fault model, where a fault coverage larger than 99% is also achieved in any case.

An effective built-in self-test (BIST) scheme for parallel multipliers (array and tree) is proposed. The new scheme combines the advantages of deterministic and pseudorandom testing and avoids their drawbacks. No modifications to the multiplier structure are required. A guaranteed very high fault coverage of a comprehensive cellular fault model is achieved. The results do not depend either on the gate-level implementation of the multiplier cells or the architecture of the multiplier (whether it is a carry-propagate or carry-save array multiplier or a tree multiplier) or on the multiplier size. A small deterministic test set of highly regular test vectors is used which exploits the inherent regularity of the multiplier architecture. The regularity of the test vectors allows for their on-chip generation with a very small hardware overhead, which is equivalent to the hardware overhead of pseudorandom testing.

In this paper a novel input vector monitoring concurrent BIST technique based on a RAM (R-CBIST) is presented. This technique compares favorably to the other input vector monitoring concurrent BIST techniques proposed so far with respect to the hardware overhead and the time required for the concurrent test to be completed (concurrent test latency). R-CBIST can be used in practice for exhaustive testing of ROMs since it results in small hardware overhead whereas no need to stop the ROM normal operation is required.

Traditional combinational fault models are not sufficient to detect to most common failure mechanisms in CMOS Iterative Logic Arrays (ILAs). The Realistic Sequential Cell Fault Model (RS-CFM) provides a comprehensive, robust test methodology for ILAs. It also satisfies the requirements for low test complexity and cell implementation independence. Adopting RS-CFM, we first provide sufficient conditions for two-dimensional (2D) ILAs to be robustly testable for first time in the literature. Then, we propose sufficient modifications to the carry-save and carry-propagate array multipliers so that they can be treated robustly with respect to RS-CPM with a test set of linear size.

Multifunction arithmetic logic units (ALUs) that realize complex arithmetic and logic operations (like the operations of the 74/spl times/181 family) are widely used in today's complex integrated circuits, such as commercial microprocessors and digital signal processors. These ALUs are built around either ripple-carry (RC) adders, carry-lookahead (CLA) adders or mixed CLA/RC adders depending on area and performance requirements. In this paper, first, we introduce novel C-testable multifunction ALUs built around RC adders and linear-testable multifunction ALUs built around CLA adders and mined CLA/RC adders with respect to CFM. Then, we introduce an effective ALU BIST scheme for all three types of ALUs (RC, CLA, mixed CLA/RC) that hits the target of a unified datapath BIST architecture, since it is compatible to an effective BIST scheme for datapaths. Complete CFM testability is achieved with a reasonable number of deterministic test patterns in all cases. The scheme imposes reasonable area overhead and negligible delay overhead and owing to its inherent high regularity can be easily adopted for automatic BIST synthesis of datapaths.

Technology advances provide today the capability of integrating large Iterative Logic Arrays (ILAs) in the same chip. Traditional combinational fault models are not sufficient to detect all failures in CMOS ILAs. Robust test generation for sequential faults in ILAs has not been considered in the literature. Two-pattern tests for sequential fault detection in ILAs can be invalidated either at the cell level due to arbitrary delays inside the cells or at the array level due to the appearance of glitches at the cell inputs. A realistic sequential fault model for any type of ILA is introduced. The fault model along with algorithms for the elimination of glitches in one-dimensional ILAs provide a comprehensive methodology for robust sequential fault testing. C-testability and linear-testability are seeked to provide efficient test sets. Results of the implementation of the method on a comprehensive set of benchmark one-dimensional ILAs are provided. Test complexity and thus test cost is greatly reduced compared to exhaustive two-pattern testing proposed in the past for sequential fault testing in ILAs.

Datapath architectures are widely used in today's complex integrated circuits, such as commercial microprocessors or specialized digital signal processors. A very effective BIST scheme for general datapaths is introduced in this paper. This scheme requires the register transfer (RT) level description of a datapath design, since it is independent of specific implementations of the functional modules. The novel BIST scheme is generic, i.e. independent of the datapath width. Hence, it is well suited for fixed-width datapaths that suffer from testability problems due to the truncation of the low order half part of multiplications. A simplified version of the scheme can also be applied to non fixed-width datapaths. The deterministic BIST patterns applied, always guarantee more than 99% fault coverage, for the entire datapath, within few hundreds of clock cycles. This result is achieved by exploiting the inherent operational parallelism of datapaths. The scheme imposes small area overhead and near-zero delay overhead.

In this paper an asynchronous TSC two-rail code error indicator is presented. Such an error indicator memorises error indications {00,11} generated by TSC checkers with time duration greater than a tolerant limit T and can be used to detect not only faults that cause logical errors bat also faults that cause additional delays. Thus, concurrent detection, of delay faults inside the checkers is an additional application of the proposed circuit. The proposed TSC error indicator is more efficient than the TSC error indicator presented by Gaitanis (see IEEE Trans. Comput., vol. 34, no. 8, p. 753-61, 1985) which, to the authors' knowledge, is the only existing TSC error indicator in the open literature.

A Totally Self Checking (TSC) reconfigurable duplication system with respect to single cell fault model is described in this paper. It consists of two identical functional self checking units that receive the same inputs. TSC checkers are associated with each functional unit and produce either a normal indication when the output is correct or an error indication when the output is incorrect. The circuit that receives the indications of the two TSC checkers is a TSC decision circuit that produces two indication outputs E and F, respectively. E indicates mainly the status of the outputs of units while F indicates the existence of internal faults in the TSC decision circuit. Such indications can be used for the non stop repair before redundancy is exhausted. Thus continuous operation is preserved increasing the availability and the reliability of the system.

Array multipliers, due to their high regularity, are efficiently designed as parts of complex VLSI devices. Such embedded multipliers have low controllability and observability, making the use of appropriate BIST schemes a necessity. This paper introduces a very effective BIST scheme for carry-propagate and carry-save array multipliers. The deterministic BIST patterns produced by the Test Pattern Generator provide a fault coverage larger than 99%. The required Test Pattern Generator consists of a simple binary counter or maximum length LFSR of a fixed size (8-bits), independent of the size of the multiplier. For Output Data Evaluation a count-based scheme is adopted. The novel BIST scheme does not require any DFT in the multiplier design and is generic, i.e. independent of specific implementations of the multiplier cells.

Built-In Self-Test (BIST) techniques constitute an attractive and practical solution to the difficult problem of testing VLSI circuits and systems. Among the BIST techniques the Comparative Concurrent BIST (C-BIST) has various advantages since it provides for off-line test generation, when it is desirable, and thus accomplishes a mixed on-line/off-line BIST scheme. However, in C-BIST when the test sequence is long, the time required for all the test vectors to appear among the normal inputs to the circuit (test latency) is significantly long. Modifications of the C-BIST technique have been proposed in order to reduce the test latency. In this paper we propose a new C-BIST technique termed windowed-CBIST (w-CBIST) for test latency reduction. The proposed technique is shown to be significantly more efficient from the previous methods with respect to test latency and hardware overhead.

Booth multipliers are widely used in both general purpose datapath structures and specialized Digital Signal Processors. Such multipliers when embedded in complex ICs have low controllability and observability, so the use of a suitable BIST scheme is a necessity. No Such BIST schemes for Booth multipliers are available to our knowledge in the open literature. A very effective BIST scheme for Booth multipliers is introduced. The algorithmic BIST patterns that this scheme generates guarantee >99% fault coverage. The required Test Pattern Generator consists of a simple fixed-size binary counter or maximum length LFSR, independent of the site of the multiplier. Several count-based compaction schemes are evaluated and a new such compaction scheme is found to be the most effective. The novel BIST scheme is generic, i.e., independent of specific implementations of the multiplier cells and does not require DFT in the multiplier design. Due to its effectiveness and regularity this BIST architecture was adopted for automatic BIST synthesis via the parameterized multiplier generation tool.

In this paper we give the fundamental theory for testing one or two-dimensional Iterative Logic Arrays (ILAs) with respect to realistic faults requiring two-pattern or generally n-pattern tests. We give conditions so that C-testability and linear-testability are preserved. According to our approach the extensive work made for ILAs under the Cell Fault Model can be easily used to derive an efficient test set of an ILA for more realistic faults.

Paschalis et al. (1988) have given a structured method to design TSC m-out-of-2m code checkers suitable for VLSI implementation. In this correspondence we give sufficient conditions so that the method previously given can be used to design checkers for classes of m-out-of-n codes with n/spl ne/2m.>

In this paper a new method to design totally self-checking (TSC) checkers for a class of Borden codes is given and their applicability is discussed. The TSC checkers designed in this paper are impressively more efficient, with respect to implementation cost and speed, than the corresponding checkers hitherto proposed in the literature.>

A description of the conformance test system for the pan-European paging system ERMES is presented. This test system has been developed for checking the ERMES receivers for conformity to the relevant air interface and receiver operation standard specification according to the ISO 9646 standardized methodology for conformance testing services.>

The paper deals with the physical layer conformance testing of the Digital European Cordless Telecommunications (DECT) system. The abstract test suite, the test system and an automated test realization process are described in accordance with the OSI conformance testing methodology and framework (ISO/TEC 9646). The proposed test system has been adopted by the test laboratories which are going to provide a conformance test service on DECT equipment in Europe.>

A design method for a combinational totally self-checking (TSC) 1-out-of-3 code checker is presented. This method is not only simpler and more efficient than others, but is also successful in the case where more than one 1-out-of-3 code exists in a TSC system.>

A method is proposed that is based on the partitioning of the input code variables into two sections, each section representing the binary form of a number Z/sub 1/ and Z/sub 2/, respectively. For a code with check base A=2/sup m/-1, two m-bit end-around carry adder trees calculate the modulo m residue of Z/sub 1/ and Z/sub 2/, while a totally self-checking (TSC) translator maps the output of the pair of trees onto m-variable two-rail code. A TSC two-rail checker maps the m-variable two-rail code onto one-out-of-two code. The checkers present significant improvement in the implementation cost, number of gate levels, and reliability over TSC checkers previously proposed in the literature.>

A design method of totally self-checking (TSC) m-out-of-2m code checkers is presented. The design is composed basically of two full-adder/half-adder trees, each summing up the ones received on m input lines, and a k-variable two-pair two-rail code tree that compares the outputs of the two-adder tree. The only modules used are full-adders, half-adders, and two-variable TSC two-rail code checkers. This method is well suited for VLSI MOS implementation and, compared to previous methods, it results in significant circuit cost reduction and smaller test set, without sacrificing performance. Also, the proposed design has the advantages of a modular design.>