Article Free Access Share on Configuration cloning: exploiting regularity in dynamic DSP architectures Authors: S. R. Park Dept. of ECE, University of Massachusetts, Amherst, MA Dept. of ECE, University of Massachusetts, Amherst, MAView Profile , W. Burleson Dept. of ECE, University of Massachusetts, Amherst, MA Dept. of ECE, University of Massachusetts, Amherst, MAView Profile Authors Info & Claims FPGA '99: Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arraysFebruary 1999 Pages 81–89https://doi.org/10.1145/296399.296433Published:01 February 1999Publication History 7citation322DownloadsMetricsTotal Citations7Total Downloads322Last 12 Months7Last 6 weeks4 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Motion estimation presents a class of algorithms well-suited to reconfigurable hardware due to their variable computational load, highly structured array architectures, robust reduced complexity algorithms, and a motivation for low power implementations in portable video products. Motion estimation is the most computationally demanding part of video compression algorithms and hence usually requires hardware support for real-time implementation. However, dedicated hardware usually requires that the algorithm and most of its parameters be hardwired. Reconfigurable hardware based on FPGAs allows the parallelism of hardware implementations with the flexibility of software. The statistics of motion vectors can be monitored on a frame by frame basis to choose appropriate algorithm and hardware configurations. Unlike some proposed applications of dynamic reconfiguration, this rate can easily be supported by existing FPGA technology. Another novel aspect of this work is that we use power savings as a motivation for the reconfiguration. Although FPGAs are not a very power efficient technology; careful design of array architectures can allow power to be saved by avoiding unnecessary computation by adjusting the search area according to the changing characteristics of an input video signal. Another more general result is that further power saving can be achieved by utilizing free FPGA resources as local memory to avoid power-hungry off-chip communication. Practical implementation issues using Xilinx 6200 series FPGAs are also discussed.