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Sanjay K. Banerjee

dblp:16/6987 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1990
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 50% Electronic design automation · 50%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits
0.011990
A universal MOSFET mobility degradation model for circuit simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990
Electronic design automation
circuit simulation
0.011990
A universal MOSFET mobility degradation model for circuit simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990
Electronic design automation › circuit modeling
device model
0.011990
A universal MOSFET mobility degradation model for circuit simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990
Integrated circuit design › analog and mixed-signal circuits › device modeling
MOSFET modeling
0.011990
A universal MOSFET mobility degradation model for circuit simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990

Methods — techniques the papers use, named apart from their topics

effective mobility modeling · 0.0
YearPublicationVenuePosition
1990 A universal MOSFET mobility degradation model for circuit simulation
abstract
From the physical insights provided by the universal effective mobility versus effective vertical electric field curve for electrons in MOS inversion layers, a simple general expression for the gate voltage dependence of the effective electron mobility is derived for use in SPICE circuit simulation. This expression is quite accurate over a wide range of channel doping concentrations and gate oxide thicknesses, without the need for fitting parameters, such as the theta parameter of the current SPICE level 3 mobility degradation model. It is, therefore, a much more universal model than the present SPICE level 3 mobility expression. Furthermore, the relative accuracy of this new model compared to the current SPICE model is expected to increase at the higher vertical electric fields typical of submicrometer oxide semiconductor field effect transistors (MOSFETs).>
Greg Yeric, A. F. Tasch Jr., Sanjay K. Banerjee
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3