At-speed logic scan tests are an important tool to ensure desired quality in mobile chips. During initial test pattern bring-up, tests that exhibit an unexpectedly high Vminpose a risk of over-testing and production yield loss. This is particularly problematic if the Vminof the test is significantly higher than that of the functional system workloads. In such situations, the at-speed logic scan test is debugged to find and resolve the source of the high Vmin. This paper describes an example case study of Vmindebug, in which a series of experiments are performed to identify the root cause as individual test patterns that capture the responses of unconstrained paths. We propose pre-silicon and post-silicon methods to improve Vminby preventing problematic patterns and reducing the debug effort during test bring-up. Our methods have been verified on ATE to effectively improve Vminby 28.83mV to 39.33mV with 0% to 0.5% pattern count inflation.

In lower technology nodes, cases are rising where silicon behavior is unexpected under the applications of a traditional fault model-based test vector. For example, a Transition Delay Fault (TDF) based test vector expected to catch timing sensitive defects which should have frequency dependency. The expected behavior would be a reducing error counts (even a small passing region) with higher voltage and lower frequency. But often hard/static failures (no passing region across voltage/Frequency) are being observed with TDF pattern set. A hard failure may indicate a cell internal open defect which is accidently triggered by TDF two cycle patterns. To understand these silicon failures, it is important to generate test vectors targeting special input combinations for all the standard cells in the design. EDA industry provides the solution using the proposed ‘Cell Aware’ fault model. However, in this paper, we talk about different types of in-house custom fault modelling which can be generated in ‘logical space’. The paper talk in details of the methodology of these in-house fault models, compares them, and finally use failure analysis (FA) to prove the effectiveness of the fault model.

Diagnosing chain failures is extremely important to ramp up production yield. Use of modern day low pin compressors limit the observability making chain diagnosis a difficult problem. When multiple chains fail during initial ramp up of yield, the high-resolution patterns are generally used for diagnosis. These patterns are generated using special ATPG settings and are very high in numbers. These high-resolution patterns burden the Automatic Test Equipment (ATE) with extra test time and test memory. In this work, we have developed a new algorithm to diagnose multiple chains using compressed production test pattern set. We believe that this is the first work which exhibits the use of production patterns to diagnose multiple chains. Diagnosing one chain at a time, this algorithm applies the information obtained so far to diagnose other chains. Experimental results show that up to 10 chains can be diagnosed simultaneously using compressed production patterns.

Diagnosis with a modern day low pin convolution compressor is difficult. Generally, it is done in two steps. In the first step, known as failure mapping, failures are mapped to the scan cells from the faulty responses recorded at compressor outputs on the Automatic Test Equipment (ATE). In the second step, normal scan diagnosis - cone tracing and fault simulation - is used to identify the faulty gate/pin/net. Accurate failure mapping is extremely important for successful diagnosis. Unfortunately, due to aliasing and presence of don't cares in the response, no mapping algorithm can guarantee that mapping will always be correct for convolution compressors. In this paper, we proposes a new technique which can handle incorrect mappings (the first step of diagnosis). This feature is shown to provide significant improvement over previous methods. Combining the new proposed techniques to the prior algorithms, we have achieved scan level diagnosis accuracy (99.8%) in a compression environment with extreme low pin compressors.

The temperature of a block (a region in the chip) depends on both heat generation (caused by power consumption) and heat dissipation among neighbors. Power aware test solutions targeting low power consumption during testing, may not produce an acceptable thermal aware solution. In this paper, a hardware based solution using an AND-OR block between the decompressor and each scan chain, has been utilized to deactivate some scan chains during loading to reduce peak temperature during testing. The proposed schemes require negligible hardware overhead and do not require any special patterns. Experimental results of our proposed approach on ISCAS'89 and ITC'99 benchmark circuits show a good reduction in peak temperature.

Diagnosis is extremely important to ramp up the yield during the integrated circuit manufacturing process. It reduces the time to market and product cost. Limited observability due to test response compaction negatively affects the diagnosis procedure. When multiple chains, mapped to a single compactor, fail, diagnosis becomes extremely difficult. The procedure is even more complicated because when a circuit fails the flush test, not all the patterns are applied. Only a few of the patterns are applied and the observed responses are used to diagnose the faulty chains. In this paper, we have proposed an efficient masking strategy that will be very useful for diagnosis of scan chains when multiple scan chains fail. The proposed strategy uses the redundancy in fault detection by the test patterns and masks scan chains in such a way that enough information can be provided with small increase in test pattern count. A new tester architecture that will select and apply only those patterns having enough information for diagnosis has also been proposed. Diagnostic resolution and first hit index achieved by our method are very close to their ideal values, which validate the applicability of our approach.

This brief proposes a framework to analyze multiple faults based on multiple fault simulation in a particle swarm optimization environment. Experimentation shows that up to ten faults can be diagnosed in a reasonable time. However, the scheme does not put any restriction on the number of simultaneous faults.

Temperature during testing has become an important issue to be considered with the continuous improvement of VLSI technology. As increase in temperature during testing causes permanent or temporal damage of the chip, reduction in peak temperature of the chip becomes necessary. Also to bring uniformity in temperature distribution across the chip the thermal variance needs to be reduced. Temperature of a block depends on both heat generation caused by power consumption and heat dissipation among neighboring blocks in the circuit under test (CUT). Heat generation can be reduced by reducing transitions among test vectors. However, heat dissipation depends on thermal gradient. To reduce the peak temperature and thermal variance, the don't care bits present in test vectors can be filled in such a way that the transitions of a block and also of its neighbors get reduced. In this paper we have proposed a don't care filling technique which fills the don't care bits in the test vectors in a way such that peak temperature and thermal variance as well as the peak power and average power get reduced. Experimental results of our proposed approach on ISCAS'89 benchmark circuits show an enriched reduction in peak temperature and thermal variance as well as in peak power and average power with nominal CPU time.

Volume Diagnosis is extremely important to ramp up the yield during the IC manufacturing process. Limited observability due to test response compaction negatively affects the diagnosis procedure. Hence, in a compaction environment, it is important to implement Design For Diagnosis (DFD) methodology to restore diagnostic resolution. In this paper, a novel DFD technique which makes the faulty chains to behave as good chains during loading, has been proposed. As a result, the errors introduced in the responses, must occur during unloading of the scan chains. Diagnosis can then be performed by directly comparing the actual and expected responses without any fault simulation - leading to significant reduction in time. Results on benchmark circuits show that the average number of suspected cells for single chain failure is 1.27 (ideal value being 1) and the time taken for diagnosis is in the order of milli-seconds.

When multiple chains, mapped to the same compactor output fail, AND-gate masking logic at the compactor side can be used to aid in diagnosis. The basic idea is: if for some pattern, only one faulty chain is observed and all the other faulty chains are masked, then the corresponding compacted response will only be affected by the non-masked faulty chain. Such a test pattern will help to diagnose that chain.

This paper introduces a new metric to characterize test sets in terms of their diagnostic power. Our method uses much less space compared to the existing ones and is quite accurate. The metric can be utilized to increase the diagnosability of incompletely specified test sets via don't care filling. The X-filling approach can be integrated with test pattern generation tools to aid in better diagnostic pattern set generation.

In this paper we present a method to identify don't care locations in a fully specified set of vectors, considering both fault propagation path and fault activation path. We exploit the identified X bits to convert the original vector to low power vector by dictionary based approach to minimize both dynamic and runtime leakage power. The dynamic power as well as the runtime leakage power depends on the activity in the circuit and hence depends on the sequence in which the test vectors are fed to it. We present an approach based on Particle Swarm Optimization (PSO) for vector reordering. Experiments on ISCAS89 benchmark circuits validate the effectiveness of our work. We achieve a maximum of 86.63% at an average of 60.89% reduction in dynamic power, a maximum of 6.87% at an average of 5.28% savings in terms of leakage power and a maximum of 66.55% at an average of 50.11% savings in terms of total power with respect to the original compacted test set generated by Tetramax ATPG tool.

Test mode power dissipation has been found to be much more than the functional power dissipation. Since dynamic power dissipation had a major contribution to the heat generated, most of the studies focused on reducing the transitions during testing. But at submicron technology, leakage current becomes significantly high. This demands a control on the leakage current as well. In this work, we propose techniques to simultaneously reduce the switching activity and keeping the leakage current under check. The overall average switching activity reduction is 70.01% and reduction in leakage power is about 6.31%, the maximum being 99.33% in switching and 9.92% in leakage.