This session consists of three industry papers invited for their viewpoints on the challenges on future needs for low-power electronic design from an industry perspective. The authors are experts on the field of low-power design techniques as well as in CAD tools for implementing these techniques, both areas that are critical to actually achieving the goals of aggressive chip design. In addition, the authors provide a perspective of the lessons learned and the evolution of the techniques that have enabled mobile platforms to become so widely deployed and a big part of our everyday lives.

VLSI engineers have traditionally used a variety of CAD analysis tools (e.g. SPICE) to deal with variability.As we go into deep sub micron issues, the analysis is becoming harder due to many secondary effects becoming primary. Panelists will debate the variability trend and present the order of importance of many variability trends (Vdd, Vt, Interconnect, Leff, Gate Width) and their impact on design tools and methodologies.What new design tools, new modeling methodologies, and new (or old) design styles will combine to address variability?Will conservative design to accommodate variability halt the progress of Moore's Law?Is life as we know it over, or are we facing an opportunity for innovation in tools and design that will move us forward over the barriers that technology has placed in our path?.

Historically, Back End of Line (BEOL) or interconnect resistance and capacitance have been viewed as parasitic components. They have now become key parameters with significant impact on circuit performance and signal integrity. This paper examines the types of BEOL variations and their impact on RC extraction. The importance of modeling systematic effects in RC extraction is discussed. The need for minimizing the computational error in RC extraction before incorporating random process variations is emphasized.

Process variations - which affect critical electrical parameters and lead to both random and systematic changes in circuit performance - have always posed significant challenges to semiconductor design. In the past, within-die process variation was relatively small, and methods such as corner-based analysis were sufficient. This allowed timing analysis tools to calculate delays, slew times, coupling and power in a straightforward way. Today, the International Technology Roadmap for Semiconductors suggests that the semiconductor industry's historical ability to control process variations is under siege, for both devices and interconnects. As statistical variation increases, will corner-casing lead to too much conservatism, and hence a requirement for new statistical timing and noise analysis tools? In other words, is the design flow inevitably moving to "delay is no longer a number; it's a distribution"? Or are the urgency and the advantages of statistical timing analysis overstated.

This paper is in response to the question 'ASIC Design the nm era - dead or alive' from an ASIC library architecture and library flow point of view. The authors believe it is certainly significantly harder to design in the nm era but ASIC design is not dead. ASIC Design is much more challenging in the nanometer era. This paper will present some of the main effects that have become significant in terms of library architecture and library creation flow. Some full chip level effects will be discussed. Example solutions to some of these dramatic trends will also be presented. This is presented in a 'stories from the trenches' format - from the team that architects and delivers TI ASIC libraries. The majority of the data presented comes from development of TI ASIC 130, 90 and 65nm libraries.