Connected and Automated Vehicles (CAVs) have real-time information from the surrounding environment by using local on-board sensors, V2X (Vehicle-to-Everything) communications, pre-loaded vehicle-specific lookup tables, and map database. CAVs are capable of improving energy efficiency by incorporating these information. In particular, Eco-Cruise and Eco-Lane Selection on highways and/or motorways have immense potential to save energy, because there are generally fewer traffic controllers and the vehicles keep moving in general. In this paper, we present a cooperative and energy-efficient lane-selection strategy named MultiCruise, where each CAV selects one among multiple candidate lanes that allows the most energy-efficient travel. MultiCruise incorporates an Eco-Cruise component to select the most energy-efficient lane. The Eco-Cruise component calculates the driving parameters and prospective energy consumption of the ego vehicle for each candidate lane, and the Eco-Lane Selection component uses these values. As a result, MultiCruise can account for multiple data sources, such as the road curvature and the surrounding vehicles' velocities and accelerations. The eco-autonomous driving strategy, MultiCruise, is tested, designed and verified by using a co-simulation test platform that includes autonomous driving software and realistic road networks to study the performance under realistic driving conditions. Our experimental evaluations show that our eco-autonomous Mul-tiCruise saves up to 8.5% fuel consumption.

With advances in sensing, computing and communication technologies, Connected and Automated Vehicles (CAVs) are becoming feasible. The advent of CAVs presents new opportunities to improve the energy efficiency of individual vehicles. However, testing and verifying energy-efficient autonomous driving systems are difficult due to safety considerations and repeatability. In this paper, we present a co-simulation platform to develop and test novel vehicle eco-autonomous driving technologies named InfoRich, which incorporates the information from on-board sensors, V2X communications, and map database. The co-simulation platform includes eco-autonomous driving software, vehicle dynamics and powertrain (VD&PT) model, and a traffic environment simulator. Also, we utilize synthetic drive cycles derived from real-world driving data to test the strategies under realistic driving scenarios. To build road networks from the real-world driving data, we develop an Automated Parser and Calculator for Map/Scenario named AutoPASCAL. Overall, the simulation platform provides a realistic vehicle model, powertrain model, sensor model, traffic model, and road-network model to enable the evaluation of the energy efficiency of eco-autonomous driving.

Modern automobiles with driving-assist features are inherently safety-critical. Strict safety requirements and the introduction of self-driving capabilities have increased the demands on the computing and communication systems within automobiles. The AUTomotive Open System ARchitecture (AUTOSAR) Adaptive platform aims to meet these industry requirements by supporting high-performance computing devices and high-bandwidth communication technologies. The AUTOSAR Adaptive platform leverages Scalable service-Oriented MiddlewarE over IP (SOME/IP), an automotive middleware solution, that supports the exchange of control messages across various devices of different sizes and operating systems. Typically, in order to guarantee the safe execution of software, automobiles employ redundancy for crucial software tasks to tolerate permanent crash faults. The Adaptive AUTOSAR standard does not specify any fault-tolerance requirements. In this paper, we highlight some gaps in the current AUTOSAR Adaptive Platfrom standard (version 18.10) and provide suggestions to address them. We present our framework to support fault-tolerant execution using different replication strategies for the AUTOSAR Adaptive Platform. We analyze the fault detection and recovery-time bounds of our solution for applications using SOME/IP. We validate our model experimentally and present our evaluation results.

Safety-critical real-time systems like modern automobiles with advanced driving-assist features must employ redundancy for crucial software tasks to tolerate permanent crash faults. This redundancy can be achieved by using techniques like active replication or the primary-backup approach. In such systems, the recovery time which is the amount of time it takes for a redundant task to take over execution on the failure of a primary task becomes a very important design parameter. The recovery time for a given task depends on various factors like task allocation, primary and redundant task priorities, system load and the scheduling policy. Each task can also have a different recovery time requirement (RTR). For example, in automobiles with automated driving features, safety-critical tasks like perception and steering control have strict RTRs, whereas such requirements are more relaxed in the case of tasks like heating control and mission planning. In this paper, we analyze the recovery time for software tasks in a real-time system employing Rate-Monotonic Scheduling (RMS). We derive bounds on the recovery times for different redundant task options and propose techniques to determine the redundant-task type for a task to satisfy its RTR. We also address the fault-tolerant task allocation problem, with the additional constraint of satisfying the RTR of each task in the system. Given that the problem of assigning tasks to processors is a well-known NP-hard bin-packing problem we propose computationally-efficient heuristics to find a feasible allocation of tasks and their redundant copies. We also apply the simulated annealing method to the fault-tolerant task allocation problem with RTR constraints and compare against our heuristics.

Due to the advent of active safety features and automated driving capabilities, the scope and complexity of embedded computing systems within automobiles continue to increase. Moreover, with the introduction of communication technologies like dedicated short range communications (DSRC), autonomous vehicles can also communicate with each other, pedestrians and the infrastructure. As the number of applications and levels of autonomy within such connected and autonomous vehicles (CAVs) increase the inherent safety-critical nature of CAVs imposes strict requirements in terms of testing and verification of system correctness. Hence, appropriate tools and methodologies are to manage these increasing complexity and testing requirements. In this paper, we present a standard reference architecture for CAVs and the tools and methodologies we use to model, design, develop and test systems to realize CAV applications.

Due to the advent of active safety features and automated driving capabilities, the complexity of embedded computing systems within automobiles continues to increase. Such advanced driver assistance systems (ADAS) are inherently safety-critical and must tolerate failures in any subsystem. However, fault-tolerance in safety-critical systems has been traditionally supported by hardware replication, which is prohibitively expensive in terms of cost, weight, and size for the automotive market. Recent work has studied the use of software-based fault-tolerance techniques that utilize task-level hot and cold standbys to tolerate fail-stop processor and task failures. The benefit of using standbys is maximal when a task and any of its standbys obey the placement constraint of not being co-located on the same processor. We propose a new heuristic based on a "tiered" placement constraint, and show that our heuristic produces a better task assignment that saves at least one processor up to 40% of the time relative to the best known heuristic to date. We then introduce a task allocation algorithm that, for the first time to our knowledge, leverages the run-time attributes of cold standbys. Our empirical study finds that our heuristic uses no more than one additional processor in most cases relative to an optimal allocation that we construct for evaluation purposes using a creative technique. We have designed and implemented our software fault-tolerance framework in AUTOSAR, an automotive industry standard. We use this implementation to provide an experimental evaluation of our task-level fault-tolerance features. Finally, we present an analysis of the worst-case behavior of our task recovery features.

As transistor geometries get smaller, static leakage power dominates the power consumption in modern processors. This phenomenon diminishes the ability of frequency scaling-based techniques to save energy. Modern processors also provide sleep states which minimize leakage power by gating portions of the processor and/or the system clock. This paper presents partitioned fixed-priority scheduling solutions for utilizing these sleep states to efficiently schedule periodic real-time tasks, and maximize energy savings on multi-core processors. The techniques presented rely on an Enhanced Version of Energy-Saving Rate-Harmonized Scheduling (ES-RHS), and our newly proposed Energy-Saving Rate-Monotonic Scheduling (ES-RMS) policy to maximize the time the processor spends in the lowest-power deep sleep state. In some modern multi-core processors, all cores need to transition synchronously into deep sleep. For this class of processors, we present a partitioning technique called Max-SyncSleep which utilizes a priori task information, to maximize the synchronous deep sleep duration across all processing cores. The performance of Max-SyncSleep is compared to the classical Worst-Fit Decreasing load balancing heuristic. We also illustrate the benefits of using ES-RMS over ES-RHS for this class of processors. For processors which allow cores to individually transition into deep sleep, we prove that, while utilizing ES-RHS on each core, any feasible partition can optimally utilize all of the processor's idle durations to put it into deep sleep. Experimental evaluations indicate that the proposed techniques can provide significant energy savings.

Power dissipation of an LSI circuit during scan testing, especially at-speed scan testing, can be several times higher than that during functional operations. Excessive test power causes hot spots and/or severe IR drop that may lead to chip damage, undue yield loss, or reliability degradation, especially for low-power LSI circuits. As a result, it is becoming increasingly important to reduce test power by lowering test-induced toggle activity in order to make scan test “power-safe”. However, with the stress on reducing toggle activity during scan test one might question: Have we gone too far? Should we reduce toggle activity below functional levels? Should we even plan for many test sets with different toggle activities? Can the test power problem be solved by existing DFT and ATPG solutions? What's missing in today's solutions? What's next for low-power testing? This panel provides an interactive forum to discuss these critical questions with industry experts from both semiconductor and EDA companies. It helps practitioners and researchers alike in their quest for more effective and more efficient solutions to the test power problem.