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Tsou-Han Chiu

dblp:160/0286 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2018
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Theoretical computer science
1 paper
Coding theory · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Storage systems · 77% Parallel and multicore computing · 23%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Storage systems › flash and SSD › flash memory
LDPC decoding
0.212016
Unified Designs for High Performance LDPC Decoding on GPGPU · IEEE Trans. Computers 2016
Coding theory
error-correcting codes
0.212016
Unified Designs for High Performance LDPC Decoding on GPGPU · IEEE Trans. Computers 2016
Coding theory › error-correcting codes
LDPC codes
0.212016
Unified Designs for High Performance LDPC Decoding on GPGPU · IEEE Trans. Computers 2016
Coding theory › error-correcting codes › LDPC codes
LDPC decoding
0.212016
Unified Designs for High Performance LDPC Decoding on GPGPU · IEEE Trans. Computers 2016

Methods — techniques the papers use, named apart from their topics

translation array · 0.5node-based scheme · 0.5edge-based parallel paradigm · 0.5
YearPublicationVenuePosition
2018 Towards high performance data analytic on heterogeneous many-core systems: A study on Bayesian Sequential Partitioning
Bo-Cheng Lai, Tung-Yu Wu, Tsou-Han Chiu, Kun-Chun Li, Chia-Ying Lee, Wei-Chen Chien, Wing Hung Wong
J. Parallel Distributed Comput.3
2016 Unified Designs for High Performance LDPC Decoding on GPGPU
abstract
Modern GPGPU's have enabled massively parallel computing with programmability that can exploit the highly parallel nature of LDPC decoding. Previous works customized the design on a GPGPU towards specific execution attributes of a particular LDPC decoding matrix. Supporting different LDPC decoding matrices requires either substantial rework on the current program, or a brand new parallel design. This paper proposes two unified designs that can achieve high performance for both regular and irregular LDPC decoding on a GPGPU. The first design introduces a node-based scheme with a versatile translation array mechanism that can efficiently handle the complex data access patterns of different LDPC decoding matrices. The second design proposes an edge-based parallel paradigm that uses more intuitive data layout. More edges than nodes in a Tanner graph also give the edge-based design higher computation parallelism when there are limited concurrent codewords. With the proposed unified designs, designers can be ignorant of the types of LDPC matrices and achieve high performance LDPC decoding. The experiments on a GTX 470 GPGPU have demonstrated up to 134.56x runtime improvement, when compared with designs on a high-end CPU. The maximum throughput can reach 80.25 Mbps. When compared with the previous customized designs, the proposed systematic designs can reach better performance while relieving the effort of customization.
Bo-Cheng Lai, Chia-Ying Lee, Tsou-Han Chiu, Hsien-Kai Kuo, Chun-Kai Chang
IEEE Trans. Computers3