This paper presents a position estimation method for shape-changing user interfaces composed of multiple small modules. The method employs compact resonant coils for both communication and position estimation based on received signal strength. When a small coil resonates at a high frequency, the magnetic field exhibits both inductive and radiative characteristics. Our method analyzes the magnetic field through electromagnetic simulation and leverages this relationship for position estimation. The proposed method is robust against occlusion, does not require external cameras or sensors, and enables position estimation solely from communication characteristics. Furthermore, compared to conventional electromagnetic induction-based methods, it supports longer-range communication and position estimation while achieving an average error on the order of millimeters.

Real-time Quantum Error Correction (QEC) for Fault-Tolerant Quantum Computing (FTQC) demands immediate surface code decoding with both high accuracy and low latency. The highly accurate Union-Find (UF) algorithm has traditionally been limited to batch-processing, as its iterative cluster growth is incompatible with the concurrent initiation of decoding with each syndrome measurement round, required for real-time QEC. This research presents a novel online UF decoder microarchitecture designed to overcome these limitations. Our key innovation decomposes UF cluster growth into incremental, per-cycle steps managed by a dedicated SHIFT stage. ASIC evaluation of our implementation demonstrates a$\mathbf{1 0 2. 3 8}$ns latency for a surface code with a distance of 23 and an approximate 1.4% threshold, meeting critical QEC performance targets. By demonstrating a viable online UF decoder with competitive performance, this research offers a crucial building block for the practical realization of scalable FTQC.

Out-of-order superscalar processors achieve high performance at the cost of control complexity and energy overhead, with register renaming contributing significantly. Distancebased instruction set architectures (ISAs) provide an alternative to avoid register renaming by specifying operands using relative instruction distances. As a representative design, STRAIGHT implements this approach to support out-of-order execution and eliminate false dependencies in a lightweight design. However, to simplify the overall system design and ensure clear instruction semantics, distance-based architectures require additional instructions (e.g., RMOV) to adjust operand distances, which consume execution resources and, more critically, may delay dependent instructions, resulting in performance degradation. In this paper, we propose Register Bridging, a mechanism that redirects semantically equivalent operands to bypass RMOV dependencies, enabling parallel execution of instructions previously constrained by data-flow ordering. Specifically, a circular buffer is introduced to support operand redirecting with low complexity, in contrast to traditional renaming tables. We implemented the proposed method on a cycle-accurate simulator and compiled benchmarks using the optimizing STRAIGHT compiler. Through a series of simulation experiments on both realistic and synthetic benchmarks, we demonstrate that our proposal enables 41.9% of relay instructions to be bypassed on average, as well as improves performance by up to 5.7%, compared to related methods.

To realize a fault-tolerant quantum computer, a quantum error decoder that can handle a large number of qubits with high speed is required. This paper demonstrates an ASIC implementation of a quantum error decoder based on a greedy algorithm. The simple algorithm and microarchitecture enable a low-power and compact design. A test chip is fabricated using 22-nm CMOS technology, and its operation is verified through empirical evaluation.

The advent of shape-adaptive computers, which consist of microscale devices that can wirelessly interconnect and dynamically reconfigure their shapes and functions, presents new challenges for software development. Existing programming environments and languages are not well-suited for managing the complex state interactions and asynchronous processes inherent in such systems. In response to these challenges, we propose the design and current status of MorphLang, a declarative programming language specifically designed for shape-adaptive computers. MorphLang abstracts the complexities of device interaction, enabling developers to focus on high-level behavior definitions without the need for intricate state management. Through a practical example, we demonstrate MorphLang's ability to handle dynamic node interactions effectively, paving the way for more efficient and innovative applications in shape-adaptive computing. Our approach not only simplifies the de-velopment process but also lays the groundwork for future advancements in this emerging field.

Shape-changeable computer system is proposed as a system that forms various shapes by communicating wirelessly with many adjacent chips. A network that supports diverse shapes and dynamic chip replacement is important, and methods for constructing ad-hoc wireless networks and enabling dynamic reconfiguration of the system at runtime have been proposed so far. However, there is room for improvement in performance because they are based on up*/down* routing. Moreover, system partitioning is required by applications such as micro-robots and shape-changing user interfaces, and no network that realizes this has been studied yet. In this study, we propose a multi-tree network construction method for improving routing performance and a protocol that enables system partitioning, and we verify them by simulation using a newly-developed simulator.

The single-thread performance of a CPU is an essential factor in a computer system. However, increasing the processing width of a CPU to improve performance often results in a super-linear enlargement of the circuit area and, consequently, a massive increase in power consumption. In this paper, we present an out-of-order superscalar processor based on a new architecture, STRAIGHT, which overcomes the circuit area and power consumption problems. We have designed and evaluated the first real processor chip based on the STRAIGHT architecture. The processor chip was fabricated using 28nm CMOS technology, and we confirmed that it could correctly execute real programs. We evaluated its performance, circuit area, and power consumption, and as a result, demonstrated that a large processing width can be achieved in a small area using the new STRAIGHT architecture.

Out-of-order superscalar processors are currently the only architecture that speeds up irregular programs, but they suffer from poor power efficiency. To tackle this issue, we focused on how to specify register operands. Specifying operands by register names, as conventional RISC does, requires register renaming, resulting in poor power efficiency and preventing an increase in the front-end width. In contrast, a recently proposed architecture called STRAIGHT specifies operands by inter-instruction distance, thereby eliminating register renaming. However, STRAIGHT has strong constraints on instruction placement, which generally results in a large increase in the number of instructions.

We investigated the possibility of using the output voltage of magnetic resonant coupled coils to realize a distance sensing method that can be applied even when the distance between coils is long. We changed the distance between PCB boards with 1 cm coils and measured the output voltage induced in one coil when an AC voltage of the resonant frequency is input to the other coil. As a result, a correlation was confirmed between the distance between the coils and the value of the output voltage. We found that the distance between the coils can be estimated from the output voltage even when that distance is more than five times the coil diameter. This method enables distance sensing between objects simply by placing a coil on the object. This allows for the sensing of positional relationships between components used in deformable user interfaces.

In this paper, a displacement sensing method utilizing the bit-error characteristics in inter-chip wireless bus is presented. A non-contact displacement sensor is highly demanded in many engineering fields, and its miniaturization contributes to the expansion of further application areas and simplifies implementation. Inter-chip wireless bus is a short-range wireless communication technology that uses a small coupler, and its bit-error characteristics change according to the relative position between couplers. Additionally, the bit-error rate in inter-chip wireless bus can be obtained solely by digital processing through a tiny microcontroller. Therefore, a tiny digital displacement sensor, integrating a small coupler, wireless transceiver circuits, and a microcontroller, can be realized. The principle of proposed sensing method is verified using simulations, and a 1 mm × 1 mm CMOS LSI test chip is designed and fabricated using 180-nm CMOS technology.

Research on microrobot swarms and deformable user interfaces has been conducted extensively. Inductively coupled wireless bus technology has been proposed for such applications. This technology uses inductive coupling among on-chip coils to connect multiple chiplets wirelessly. By wirelessly connecting small chiplets, it is possible to construct deformable systems with various chip configurations. The prototype chip, which has a 32-bit RISC-V processor core and a wireless communication interface, is fabricated in 1.18-µm CMOS technology. The prototype validates that inductively coupled wireless data communication can be achieved between two processor chiplets.

The renaming unit of a superscalar processor is a very expensive module. It consumes large amounts of power and limits the front-end bandwidth. To overcome this problem, an instruction set architecture called STRAIGHT has been proposed. Owing to its unique manner of referencing operands, STRAIGHT does not cause false dependencies and allows out-of-order execution without register renaming. However, the compiler optimization techniques for STRAIGHT are still immature, and we found that the naive code generators currently available can generate inefficient code with additional instructions. In this paper, we propose two novel compiler optimization techniques and a novel calling convention for STRAIGHT to reduce the number of instructions. We compiled real-world programs with a compiler that implemented these techniques and measured their performance through simulation. The evaluation results show that the proposed methods reduced the number of executed instructions by 15% and improved the performance by 17%.

Various techniques, such as cache replacement algorithms and prefetching, have been studied to prevent instruction cache misses from becoming a bottleneck in the processor frontend. In such studies, the goal of the design has been to reduce the number of instruction cache misses. However, owing to the increasing complexity of modern processors, the correlation between reducing instruction cache misses and reducing the number of executed cycles has become smaller than in previous cases. In this paper, we propose a new guideline for improving the performance of modern processors. In addition, we propose a method for estimating the approximate performance of a design two orders of magnitude faster than a full simulation each time the designers modify their design.

A wireless bus for inter-chiplet communication is presented. Utilizing horizontal inductive coupling of on-chip coils, wireless connection between chiplets are established. A test chip prototyped in 0.18 μm CMOS confirms 2.0 Gb/s bus communication between horizontally arranged coils with BER of less than 10-12.

Owing to the growth of FPGA-based systems and the increasing complexity of applications, the demand for high-performance soft processors in FPGAs has increased. The performance of processors is enhanced through out-of-order (OoO) superscalar execution using a register renaming mechanism. However, the register renaming mechanism has two problems. First, it requires a register mapping table (RMT), which usually comprises a RAM with a large number of ports. A multi-port RAM is not suitable for an FPGA. Second, register renaming complicates recovery mechanisms for exceptions, such as branch mispredictions. These problems increase the usage of resources and hinder the improvement of performance. Recently, the STRAIGHT architecture was proposed to solve these problems. STRAIGHT has a unique instruction format and enables OoO execution without register renaming. This approach eliminates the RMT and makes the recovery operation more efficient. In this study, we demonstrate a high-performance OoO STRAIGHT soft processor by implementing several mechanisms for adopting the STRAIGHT architecture and fabricate the first STRAIGHT processor capable of executing practical complex programs. Compared to a state-of-the-art OoO soft processor, our processor consumes approximately 17% fewer LUTs and 10% fewer FlipFlops and achieves 15% higher performance in CoreMark, which is a standard benchmark.

Research on small-sized microrobot swarms and shape-changeable user interfaces has been conducted extensively. Wireless bus interface technology has been proposed for such applications. This technology uses inductive coupling among on-chip coils to connect multiple chips wirelessly. However, wireless bus technology has a peculiar characteristic of broadcasting data only to the chips arranged adjacently, and it is challenging to apply existing network protocols. In addition, interference with processors and peripheral circuits on the same chip has not been thoroughly investigated. In this study, the network architecture of a shape-changeable computer system utilizing the wireless bus interface is presented. Moreover, we show the measurement results of the first multi-chip processor prototype, which utilizes the wireless bus interface. The implementation method of a processor core and the interface, and an interchip network protocol from the physical layer to the network layer are shown. A deadlock-free routing path can be formed in an irregular network among multiple chips by the proposed protocol that takes into account the characteristics of the physical layer of the wireless bus interface. The prototype chip, which has a RISC-V processor core, and the wireless bus interface fabricated in 0.18-μm CMOS technology validates that wireless data communication can be achieved between two processor chips.

Herein, we propose a wireless bus interface that can connect multiple chips to form a flexible system. In the proposed bus interface, on-chip coils are formed along the outer periphery of each chip, and high-speed wireless communication between multiple chips is enabled via horizontal inductive coupling between coils. Using the proposed interface, embedded computer systems can be realized by simply combining small chips with different functions as needed and arranging them in an adjacent manner. The proposed bus interface enables variation in the relative angle between adjacent chips during operation, can be implemented in complicated shapes, and facilitates chip replacement post fabrication to achieve flexible and robust computer systems; such systems can be applied in micro-robots and wearable interfaces. In this paper, we present a theoretical analysis of electromagnetic coupling between coils, electromagnetic field simulation results, and circuit simulation results of transmitter and receiver circuits. Through the simulation conducted using 45 nm CMOS technology, we realized high-speed communication of 14.3 Gb/s with a power efficiency of 0.55 pJ/b using the proposed bus interface. We also verified the data collision detection ability of the proposed bus interface using a collision detection circuit and packet transfer based on a SerDes circuit.

In this paper, we present an out-of-order soft-core processor adopting STRAIGHT architecture. STRAIGHT has a unique instruction format in which source operands are expressed as distances from producer instructions. This eliminates the need for register renaming and eliminates a register map table (RMT), which usually consists of a large multi-port RAM. That leads to small area, low power consumption, and high scalability of the front-end pipeline width. Moreover, the simplified architecture enables rapid miss-recovery. The prototype is implemented and evaluated on an FPGA. Compared to an out-of-order soft-core processor with a conventional RISC ISA, the proposed soft-core consumes 147-829 fewer LUTs for the front-end pipeline. The evaluation results show that the proposed soft-core is correctly operating on an FPGA, and estimated dynamic power consumption of the soft-core is 0.120 W.

ThruChip interface (TCI) is an emerging 3-D integrated circuit stacking technology. TCI utilizes on-chip inductor to build vertical communication channel in near field distance and has been proved to stand comparison with through-siliconvia (TSV) in data rate, power, and reliability. Moreover, it is also cost-effective in manufacturing due to its wireless nature. In this paper, an analytical method is proposed to find near-optimal TCI inductive coupling channel solution. The experiment results show an average 16.8% transmitting current reduction and shrink design time from days to a few minutes.

A 1GB/s ThruChip interface (TCI) test chip for wafer thinning, power mesh, and dummy metal fill impacts are analyzed and evaluated with test chip measurement and field solver simulation. The measurement results show that TCI coil dimension can be sized down as wafer thinning by following D/Z=3 rule. However, the experiment shows 20% power reduction by enlarging TCI coil (D/Z=6). The power mesh lies between TCI coils can dramatically decrease the TCI magnetic pulse strength and hence cause TCI to fail. Dummy metal within TCI coils has no impact on TCI transmission