A D-band (114--170GHz) CMOS transceiver (TRX) chipset covering a 56GHz signal-chain bandwidth with a 640-Gb/s data rate is proposed in this work. The design includes an 8-way low-Q power-combined power amplifier (PA), a 2-way low-Q power-combined low noise amplifier (LNA), wideband-impedance-transformation mixers, and common-source-based cascaded distributed amplifiers (DA) to improve bandwidth and linearity. The proposed TRX chipset achieves a 200Gb/s SISO data rate and a 640Gb/s MIMO data rate.

A tri-mode mixer supporting the 5G NR standards over 24.25--71GHz is presented. The harmonic-selection technique reduces the local oscillator (LO) frequency range and power consumption. Besides, the proposed multiphase LO rejects unwanted harmonics. Fabricated in a 65nm CMOS process, this work consumes 12-21mW power under a 1V supply. It presents more than 20dB rejections to the undesired harmonic components at all operation bands. The required LO frequency range is only 10GHz.

An 8-Element 28-GHz time-division MIMO beamformer supporting 4x4 MIMO is presented. A fast-switching phase shifter is utilized to realize Nyquist-rate beam switching to lossless receive multiple beams by reuse single RF signal path. A prototype fabricated in 65nm CMOS achieves 64-QAM 4x4 MIMO reception in OTA measurement using four 5G NR spatial data streams with 400MHz channel bandwidth.

This paper presents a tri-mode band-selection CMOS down-conversion mixer supporting the 5G NR standards over 24.25–71 GHz. The harmonic-selection technique reduces the required local oscillator (LO) frequency range and power consumption. The second-harmonic selection mode works for the 39-GHz and 47-GHz bands, while the fundamental-selected and third-harmonic selection modes operate for the 28-GHz and 60-GHz bands, respectively. Besides, in cooperation with the proposed multi-phase LO, the mixing components behave destructively for the undesired harmonics and constructively for the desired component, which shows the rejection of unwanted harmonics. Fabricated in a 65-nm CMOS process, this work presents flat conversion gain and more than 20-dB rejections to the undesired harmonic components at all operation bands. The required LO frequency range is only 10 GHz. Occupying a core area of 0.0077 mm2, the proposed mixer consumes power of 12-21 mW in three modes under a 1-V supply.

This work first discusses the future directions of millimeter-wave wireless communication, based on Shannon and Friis equations. Afterward, 28-GHz and 39-GHz phased-array transceivers realized by 65nm CMOS technology are introduced, which are designed for 5G and beyond. The 28GHz phased- array transceiver is designed based on a neutralized bi-directional technique. The required chip area for the element transceiver is reduced to half. A cross-pol. leakage canceller is also implemented along with the transceiver to suppress the crosspol. leakage. Therefore, the dual-polarized 28-GHz phased-array module is capable to improve the wireless data with dual- polarized MIMO (DP-MIMO) configuration even under severe polarization coupling and rotation conditions. The measured DP-MIMO EVMs are 3.4% in both 64-QAM and 256-QAM. The 8-element 39GHz phased-array transceiver is also designed based on the compact bi-directional architecture. The Doherty technique is utilized in TX mode to increase the power efficiency at power backoff region. A 64-element transmitter array realizes a saturated output EIRP of 55.2dBm. To improve the phased- array performance under digital pre-distortion (DPD), an inter- element mismatch compensation technique is further employed. By utilizing the proposed mismatch compensation, the measured 64-QAM OFDMA-mode EVM and ACLR with the shared-look- up-table (shared-LUT) DPD are improved from -22.4dB to - 25.0dB and from -28.7dBc to -32.1dBc, respectively.

A 300GHz CMOS-only wireless transceiver that achieves a maximum data rate of 34Gb/s while consuming a total power of 0.41W from a 1V supply is introduced. A subharmonic mixer with low conversion loss is proposed to compensate the absence of the RF amplifiers in TX and RX as a mixer-last-mixer-first topology is adopted. The TRX covers 19 IEEE802.15.3d channels (13-23, 39-43, 52-53, 59).

This paper presents high-accuracy phase and amplitude detection circuits for the calibration of 5G millimeter-wave phased array beamformer systems. The phase and amplitude detection circuits, which are implemented in a 65nm CMOS process, can realize phase and amplitude detections with RMS phase error of 0.17 degree and RMS gain error of 0.12 dB, respectively. The total power consumption of the circuits is 59mW.

An energy efficient digital polar transmitter (TX) based on 1.5bit Delta-Sigma modulator (DSM) and fractional-N injection-locked phase-locked loop (IL-PLL) is proposed. In the proposed TX, redundant charge and discharge of turned-off capacitors in the conventional switched-capacitor power amplifiers (SCPAs) are avoided, which drastically improves the efficiency at power back-off. In the PLL, spur-mitigation technique is proposed to reduce the frequency mismatch between the oscillator and the reference. The transmitter, implemented in 65nm CMOS, achieves a PAE of 29% at an EVM of -25.1dB, and a system efficiency of 23.8%.

A phase shifter with temperature compensation for 28GHz phased-array TRX is presented. A precise low-voltage current reference is proposed for the IDAC biasing circuit. The total gain variation for a single TX path including phase shifter and post stage amplifiers over -40°C to 80°C is only 1dB in measurement and the overall phase error due to temperature is less than 1 degree without off-chip calibration.

In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-Nmultiplying delay-locked loop(MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a variable-slope DTC is used as the fine stage. To calibrate the DTC nonlinearity, a highly robust zero-order interpolation based nonlinearity calibration is proposed. Besides, the static phase offsets (SPO) between bang-bang phase detector (BBPD) and multiplexer (MUX) are calibrated by a proposed hybrid analog/digital phase offset calibration, while the dynamic phase offsets (DPO) are removed by a proposed complementary switching scheme. The co-design of the analog circuits and digital calibrations enable excellent jitter and spur performance. The MDLL achieves 0.70 and 0.48ps root-mean-square (RMS) jitter in fractional-N and integer-N modes, respectively. The fractional spur is less than -59.0dBc, and the reference spur is -64.5dBc. The power consumptions are 1.85mW and 1.22mW, corresponding to figures of merit (FOM) of -240.4dB and -245.5dB.

This article presents a small-area Bluetooth Low-Energy (BLE) transceiver (TRX) for short-range Internet-of-Things (IoT) applications in 65-nm CMOS. An integrated Radio-Frequency Input-Output (RFIO) circuitry embedded with transmitter/receiver (TX/RX) switch function and on-chip impedance matching is proposed. A hybrid-loop TRX structure based on a wide-bandwidth fractional-N digital phase-locked loop (DPLL) is implemented to achieve the maximum power reduction. A -94dBm receiver sensitivity is achieved with 2.3mW receiver power consumption, while a RF receiving bypass route integration enhances the input power tolerance. The BLE transceiver delivers -6dBm output power while consuming 2.6mW and delivers 0dBm output power while achieving 18.5% maximum TX efficiency. Thanks to the RFIO with harmonic suppression, -56dBc of 2nd-order harmonic distortion (HD2) and -48dBc of 3rd-order harmonic distortion (HD3) suppression are achieved with 0.85mm2on-chip area. This transceiver satisfied the BLE radio specification without the need for external filters and with low-power consumption, which enables minimum size and long life-time modules.

A 28GHz differential bi-directional amplifier in a standard 65nm CMOS process is presented. This work is realized based on the neutralized bi-directional core together with the fully shared inter-stage matching networks. The core chip area is only 0.11mm2. At 28GHz, a 15.1-dBm saturation output power and a 4.2-dB noise Figure are realized for PA mode and LNA mode, respectively. The DC power consumptions for PA mode and LNA mode are 149mW and 31mW, respectively, under 1-V DC supply.