Surface defect detection is essential for maintaining quality in manufacturing as it helps ensure product reliability and reduces material waste. While AI-driven visual inspection in manufacturing offers promising automation, to achieve high performance, it demands large, diverse and annotated datasets, which are often impractical to collect specially in low-volume or additive manufacturing contexts. Traditional defect detection methods relying on manual inspection and physical sensors can be labor-intensive, costly, and subject to variability. This study introduces a validated scalable pipeline for generating synthetic image datasets tailored for AI-based surface defect detection. Our pipeline integrates 3D modeling in Blender, procedural defect simulation, randomized rendering, and annotation generation to produce synthetic datasets with controlled variations in lighting, camera angles, and defect morphology. Cylindrical components were selected as the test geometry due to their industrial relevance and predictable curvature for defect propagation. To validate the pipeline, synthetic images were used to train a YOLOv8-based instance segmentation model, which was then applied, without retraining, to images of 3D printed physical parts. The trained model achieved 88% accuracy and 90% precision on the real object test dataset, demonstrating strong generalization and validating the realism and utility of the generated synthetic data. This research provides a scalable, low-cost approach for developing AI inspection systems without the need for labor-intensive real-world data collection. By bridging simulation and deployment through 3D printed physical validation, this pipeline contributes a practical foundation for synthetic-data-driven quality assurance in smart manufacturing environments.

High-speed packet switching (HPS) systems can Provide flexible, economical, high-quaiity services for integrated voice, video, and data communications. To realize such HPS systems, methods have been developed to bring about high-speed protocol processing as well as a system architecture for facilitating high-throughput switching. Adopting the parallel processing algorithm into protocol processing allows us to achieve high-speed packet protocol processing of about 100 times faster than conventional processing. Furthermore, a fully distributed system architecture in addition to hierarchical interconnection networks can achieve high-capacity packet switching systems. The proposed HPS system is thus capable of accommodating lines of up to 10-50 Mbits/s, of providing high-throughput switching capability of 1 000 000 packets/s, and of having an average delay of less than 2 ms. Furthermore, an evaluation of network delay performances of video conferencing and voice communications indicate that HPS systems are quite suitable for handling such multimedia communications.