Demo Data from VLDB 2026 / reviewers in the wild / expert
Avriti Chauhan
dblp:162/9561
· DBLP profile ↗
7ranked-venue papers
0as first author
1since 2021 · last 2024
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 7 · 1 since 2021Theory of computation · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
2 papers |
Program verification · 62% Program analysis · 20% Software testing · 18% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Program verification › model checking
bounded model checking |
0.6 | 2 | 2019 | VeriAbs : Verification by Abstraction and Test Generation · ASE 2019 Eliminating Static Analysis False Positives Using Loop Abstraction and Bounded Model Checking · FM 2015 |
Program verification
model checking |
0.4 | 1 | 2019 | VeriAbs : Verification by Abstraction and Test Generation · ASE 2019 |
Program verification › model checking › state space exploration
reachability analysis |
0.4 | 1 | 2019 | VeriAbs : Verification by Abstraction and Test Generation · ASE 2019 |
Software testing
test generation |
0.4 | 1 | 2019 | VeriAbs : Verification by Abstraction and Test Generation · ASE 2019 |
Program analysis › static analysis › bug detection
false positive reduction |
0.2 | 1 | 2015 | Eliminating Static Analysis False Positives Using Loop Abstraction and Bounded Model Checking · FM 2015 |
Program analysis
static analysis |
0.2 | 1 | 2015 | Eliminating Static Analysis False Positives Using Loop Abstraction and Bounded Model Checking · FM 2015 |
Methods — techniques the papers use, named apart from their topics
test generation · 0.4explicit-state model checking · 0.4bounded model checking · 0.4abstraction · 0.4loop abstraction · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | Navigating Confidentiality in Test Automation: A Case Study in LLM Driven Test Data GenerationabstractIn out sourced industrial projects for testing of web applications, often neither the application to be tested, nor its source code are provided to the testing team, due to confidentiality reasons, making systematic testing of these applications very challenging. However, textual descriptions of such systems are often available. So, one can consider leveraging a Large Language Model (LLM) to parse these descriptions and synthesize test generators (programs that produce test data). In our experience, LLM synthesized test generators suffer from two problems:- (1) unsound: the generators might produce invalid data and (2) incomplete: the generators typically fail to generate all expected valid inputs. To mitigate these problems, we introduce TestRefineGen a method for autonomously generating test data from textual descriptions. TestRe-fineGen begins by invoking an LLM to parse a given corpus of documents and produce multiple test gener-ators. It then uses a novel ranking approach to identify generators that can produce invalid test data, and then automatically repairs them using a counterexample-guided refinement process. Lastly, TestRefineGen per-forms a generalization procedure that offsets synthesis or refinements that leads to incompleteness, to obtain generators that produce more comprehensive valid in-puts. We evaluated the effectiveness of TestRefineGen on a manually curated set of 256 textual descriptions of test data. TestRefineGen synthesized generators that produce valid test data for 66.01 % of the descriptions. Using a combination of post-processing sanitisation and refinement it was able to successfully repair synthesized generators, which improved the success rate to 76.95 %. Further, our statistical analysis on a small subset of synthesized generators shows that TestRefineGen is able to generate test data that is well distributed across the input space. Thus, TestRefineGen can be an effective technique for autonomous test data generation for web testing in projects with confidentiality concerns. Hrishikesh Karmarkar, Supriya Agrawal, Avriti Chauhan, Pranav Shete |
SANER | 3 |
| 2020 | VeriAbs : Verification by Abstraction and Test Generation (Competition Contribution)abstractAbstract VeriAbs is a strategy selection based reachability verifier for C code. It analyzes the structure of loops, and intervals of inputs to choose one of the four verification strategies implemented in VeriAbs. In this paper, we present VeriAbs version 1.4 with updates in three strategies. We add an array verification technique called full-program induction, and enhance the existing techniques of loop pruning, k-path interval analysis, and disjunctive loop summarization. These changes have improved the verification of programs with arrays, and unstructured loops and unstructured control flows. Mohammad Afzal 0001, Supratik Chakraborty, Avriti Chauhan, Bharti Chimdyalwar, Priyanka Darke, Ashutosh Gupta 0001, Shrawan Kumar 0001, Charles Babu M, Divyesh Unadkat, R. Venkatesh 0001 |
TACAS (2) | 3 |
| 2019 | VeriAbs : Verification by Abstraction and Test GenerationabstractVerification of programs continues to be a challenge and no single known technique succeeds on all programs. In this paper we present VeriAbs, a reachability verifier for C programs that incorporates a portfolio of techniques implemented as four strategies, where each strategy is a set of techniques applied in a specific sequence. It selects a strategy based on the kind of loops in the program. We analysed the effectiveness of the implemented strategies on the 3831 verification tasks from the ReachSafety category of the 8th International Competition on Software Verification (SV-COMP) 2019 and found that although classic techniques - explicit state model checking and bounded model checking, succeed on a majority of the programs, a wide range of further techniques are required to analyse the rest. A screencast of the tool is available at https://youtu.be/Hzh3PPiODwk. Mohammad Afzal 0001, Asia A, Avriti Chauhan, Bharti Chimdyalwar, Priyanka Darke, Advaita Datar, Shrawan Kumar 0001, R. Venkatesh 0001 |
ASE | 3 |
| 2018 | VeriAbs: Verification by Abstraction and Test Generation - (Competition Contribution)
Priyanka Darke, Sumanth Prabhu S, Bharti Chimdyalwar, Avriti Chauhan, Shrawan Kumar 0001, Animesh Basak Chowdhury, R. Venkatesh 0001, Advaita Datar, Raveendra Kumar Medicherla |
TACAS (2) | 4 |
| 2017 | Efficient Safety Proofs for Industry-Scale Code Using Abstractions and Bounded Model CheckingabstractLoop Abstraction followed by Bounded Model Checking, or LABMC in short, is a promising recent technique for proving safety of large programs. In an experimental setup proposed last year [14], LABMC was combined with slicing and Iterative Context Extension (ICE) with the aim of achieving scalability over industrial code. In this paper, we address two major limitations of that set-up, namely (i) the inability of ICE to prune redundant code in a verification context, and (ii) the unavailability of a tool that implements the set-up. We propose an improvement over ICE called Iterative Function Level Slicing (IFLS) and incorporate it in our tool called ELABMC, to offer an efficient implementation of [14]. We substantiate our claim with two sets of experiments over industrial applications as well as academic benchmarks. Quantifying the benefits of IFLS over traditional ICE in one, our results report that IFLS leads to 34.9% increase in efficiency, 17.7% improvement in precision, and scales in 14.2% more cases. With the second experiment, we show that ELABMC outperforms state-of-the-art verification techniques in the task of identifying static analysis warnings as false alarms. Priyanka Darke, Bharti Chimdyalwar, Avriti Chauhan, R. Venkatesh 0001 |
ICST | 3 |
| 2017 | VeriAbs: Verification by Abstraction (Competition Contribution)
Bharti Chimdyalwar, Priyanka Darke, Avriti Chauhan, Punit Shah, Shrawan Kumar 0001, R. Venkatesh 0001 |
TACAS (2) | 3 |
| 2015 | Eliminating Static Analysis False Positives Using Loop Abstraction and Bounded Model Checking
Bharti Chimdyalwar, Priyanka Darke, Anooj Chavda, Sagar Vaghani, Avriti Chauhan |
FM | 5 |