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Chenyue Meng

dblp:163/3693 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 2018
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 52% Parallel and multicore computing · 21% Memory systems · 21%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › high-level synthesis › memory synthesis
memory partitioning
0.522018
Memory Partitioning for Parallel Multipattern Data Access in Multiple Data Arrays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018
Efficient memory partitioning for parallel data access in multidimensional arrays · DAC 2015
Memory systems › memory bandwidth
memory bandwidth optimization
0.212015
Efficient memory partitioning for parallel data access in multidimensional arrays · DAC 2015
Parallel and multicore computing › parallel computing
parallel data access
0.212015
Efficient memory partitioning for parallel data access in multidimensional arrays · DAC 2015
Reconfigurable computing and FPGAs
FPGA memory architecture
0.112015
Efficient memory partitioning for parallel data access in multidimensional arrays · DAC 2015

Methods — techniques the papers use, named apart from their topics

data splitting · 0.3conflict-free access · 0.3memory partitioning algorithm · 0.2
YearPublicationVenuePosition
2018 Memory Partitioning for Parallel Multipattern Data Access in Multiple Data Arrays
abstract
Memory bandwidth bottlenecks severely restrict parallel access of data elements from data arrays. To realize high throughput out of a relatively low bandwidth, memory partitioning algorithms have been proposed to separate data arrays into multiple memory banks, from which multiple data can be accessed in parallel. However, previous partitioning schemes only considered the case of single-pattern and single-array. In the case of multipattern and multiarray, the previous partitioning schemes will use too much time to find a partition solution and cause excessively high storage overhead. In this paper, we propose an efficient two-step memory partitioning strategy for multipattern data access in multiple arrays. First, a fast, low complexity and low overhead difference-based data splitting algorithm provides a multibank solution for multiple patterns access. Then an area-efficient bank merging algorithm merges those partitioned banks from different arrays which satisfy conflict-free requirement in order to reduce the area overhead caused by partitioning. Experimental results show that our data splitting algorithm saves up to 83.0% in searching time and reduces 39.4% storage overhead compared to the state-of-the-art approaches. With the further optimization of area-efficient bank merging, the memory area overhead are saved up to 18.9% and the total partitioning time are saved up to 45.6%.
Shouyi Yin, Zhicong Xie, Chenyue Meng, Leibo Liu, Shaojun Wei
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
2016 Multibank memory optimization for parallel data access in multiple data arrays
abstract
To realize high throughput out of a relatively low bandwidth, memory partitioning algorithms have been proposed to separate data arrays into multiple memory banks, from which multiple data can be accessed in parallel. However, previous partitioning schemes only considered the case of single-pattern and single-array. In this paper, we propose an efficient two-step memory partitioning strategy for multi-pattern access in multiple multidimensional arrays. First, a fast, low complexity and low difference-based data splitting algorithm provides a multi-bank solution for multiple patterns access. Then an area-efficiency bank merging algorithm reduce the area overhead caused by partitioning. Experimental results show that our memory splitting algorithm saves up to 83.0% in searching time finding a multi-bank solution, compared to the state-of-the-art approach and the storage overhead can be reduced by 34.5%. Meanwhile the area overheads are saved up to 18.86% and the whole partition time are saved up to 45.6% through our entire algorithm.
Shouyi Yin, Zhicong Xie, Chenyue Meng, Leibo Liu, Shaojun Wei
ICCAD3
2015 Efficient memory partitioning for parallel data access in multidimensional arrays
abstract
Memory bandwidth bottlenecks severely restrict parallel access of data from memory arrays. To increase bandwidth, memory partitioning algorithms have been proposed to access multiple memory banks simultaneously. However, previous partitioning schemes propose complex partitioning algorithms, which leads to non-optimal memory bank space utilization and unnecessary storage overhead. In this paper, we develop an efficient memory partitioning strategy with low time complexity and low storage overhead for data access in multidimensional arrays. Experimental results show that our memory partitioning algorithm saves up to 93.7% in the amount of arithmetic operations, 96.9% in execution time and 31.1% in storage overhead, compared to the state-of-the-art approach.
Chenyue Meng, Shouyi Yin, Leibo Liu, Shaojun Wei
DAC1