Although belief propagation (BP) decoders are efficient and provide significant performance for classical low-density parity-check (LDPC) codes, they will suffer a degradation in performance for quantum LDPC (QLDPC) codes due to the limitations in the quantum field. In this paper, we propose a posterior adjustment of either a single qubit or multiple qubits within binary BP. The adjustment process changes the posterior likelihood ratio for one or multiple qubits according to the designed criterion. Simulations show the performance of both single and multi-qubit adjustment is able to outperform the conventional binary BP decoder and also outperform the BP decoder concatenated with the zero-order ordered-statistics decoding (BP+OSD-0). Moreover, with lower complexity, the performance when using our proposed decoder on the considered QLDPC codes can be close to high-order OSD.

Quantum computing requires an error correction code to protect the messages against quantum noise. Surface codes are suitable for quantum error correction based on their local-qubit connection. Decoding via the conventional belief propagation (BP) algorithm is deficient for highly degenerated codes. Using the proposed block-layered sign-flipping (SF) technique, this problem can be mitigated and the error rate performance can be improved. The decoder hardware implemented for the [181, 1, 10] surface code occupies an area of 0.97 mm2and achieves a latency of 315 ns in a 90 nm process.

The job-shop scheduling problem (JSSP) is one of the best-known combinatorial optimization problems and is also an essential task in various sectors. In most real-world environments, scheduling is complex, stochastic, and dynamic, with inevitable uncertainties. Therefore, this article proposes a novel framework based on graph neural networks (GNNs) and deep reinforcement learning (DRL) to deal with the dynamic JSSP (DJSSP) with stochastic job arrivals and random machine breakdowns by minimizing the makespan. In the proposed framework, JSSP is formulated as a Markov decision process (MDP) and is associated with a disjunctive graph to encode the information of jobs and machines as nodes and arcs. We propose a GNN architecture to perform representation learning by transforming graph states into node embeddings. Then, the agent takes actions using a parameterized policy in terms of policy learning. Operations are used as actions, and an effective reward is well designed to guide the agent. We train our proposed method using proximal policy optimization (PPO), which helps minimize the loss function while ensuring that the deviation is relatively small. Extensive experiments show that the proposed method can achieve excellent results considering different criteria: efficiency, effectiveness, robustness, and generalizability. Once the proposed method is trained, it can directly schedule new JSSPs of different sizes and distributions in static benchmark tests, showing its excellent generalizability and effectiveness compared to another DRL-based method. Furthermore, the proposed method simultaneously maintains the win rate (a quantitative metric) and the scheduling score (a qualitative metric) when scheduling in dynamic environments.

Parallel machine scheduling (PMS) is a common setting in many manufacturing facilities, in which each job is allowed to be processed on one of the machines of the same type. It involves scheduling$n$jobs on$m$machines to minimize certain objective functions. For preemptive scheduling, most problems are not only NP-hard but also difficult in practice. Moreover, many unexpected events, such as machine failure and requirement change, are inevitable in the practical production process, meaning that rescheduling is required for static scheduling methods. Deep reinforcement learning (DRL), which combines deep learning and reinforcement learning, has achieved promising results in several domains and has shown the potential to solve large Markov decision process (MDP) optimization tasks. Moreover, PMS problems can be formulated as an MDP problem, inspiring us to devise a DRL method to deal with PMS problems in a dynamic environment. We develop a novel DRL-based PMS method, called DPMS, in which the developed model considers the characteristics of PMS to design states and the reward. The actions involve dispatching rules, so DPMS can be considered a meta-dispatching-rule system that can efficiently select a sequence of dispatching rules based on the current environment or unexpected events. The experimental results demonstrate that DPMS can yield promising results in a dynamic environment by learning from the interactions between the agent and the environment. Furthermore, we conduct extensive experiments to analyze DPMS in the context of developing a DRL to deal with dynamic PMS problems.

This paper presents a statistical model-fitting framework to efficiently decompose the impact of device Vt variation and power-network IR drop from the measured ring-oscillator frequencies without adding any extra circuitry to the original ring oscillators. The framework applies Gaussian process regression as its core model-fitting technique and stepwise regression as a pre-process to select significant predictor features. The experiments conducted based on the SPICE simulation of an industrial 28nm technology demonstrate that our framework can simultaneously predict the NMOS Vt, PMOS Vt and static IR drop of the ring oscillators based on their frequencies measured at different external supply voltages. The final resulting R squares of the predicted features are all more than 99.93%.

Due to the demand of pursuing a main memory with larger data bandwidth, higher data density, and lower power, the specification of DRAM has been constantly evolved in the past decade. The new DRAM specifications support multiple operating modes with multiple timing settings. It then becomes computationally infeasible to exhaustively validate all the combinations of different operating modes, timing settings and address/data with pure simulation before silicon. In this paper, we propose a framework to generate proper random patterns for validating a newly designed DDR3 SDRAM based on its first silicon chips. The proposed framework needs to not only guarantee the correctness of the generated patterns according to the state diagram and timing constraints defined in the specification but also provide the flexibility of exploring various design corners for the targeted DDR3 SDRAM. We will also show some successful silicon-validation cases of applying the proposed framework to identify the design errors based on real DDR3 SDRAM products.