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John S. Nelson

dblp:163/7758 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2003
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Integrated circuit design · 100%
Theoretical computer science
2 papers
Coding theory · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › digital circuit design
arithmetic circuit design
0.122003
New CRT-Based RNS Converter Using Restricted Moduli Set · IEEE Trans. Computers 2003
Fast Converter for 3 Moduli RNS Using New Property of CRT · IEEE Trans. Computers 1999
Integrated circuit design › digital circuit design › arithmetic circuit design
adder design
0.012003
New CRT-Based RNS Converter Using Restricted Moduli Set · IEEE Trans. Computers 2003
Integrated circuit design
digital circuit design
0.012003
New CRT-Based RNS Converter Using Restricted Moduli Set · IEEE Trans. Computers 2003
Coding theory
chinese remainder theorem
0.022003
New CRT-Based RNS Converter Using Restricted Moduli Set · IEEE Trans. Computers 2003
Fast Converter for 3 Moduli RNS Using New Property of CRT · IEEE Trans. Computers 1999

Methods — techniques the papers use, named apart from their topics

full adder optimization · 0.1fractional representation · 0.1carry-save adder · 0.0carry-propagate adder · 0.0
YearPublicationVenuePosition
2003 New CRT-Based RNS Converter Using Restricted Moduli Set
abstract
This paper presents a new RNS converter using any number of relatively prime moduli of the form 2/sup n/ and 2/sup n/ /spl plusmn/ 1. With the exception of common 3 moduli sets such as {2/sup n/ - 1,2/sup n/, 2/sup n/ + 1}, FINS output converters based on the CRT require the computation of a sum of products modulo a large number. The new converter presented in this paper uses the fractional representation for the output and eliminates the requirement for multiplications, thereby reducing area and delay. Further area improvements are possible by exploiting the period of terms to be added. An algorithmic approach is used to obtain full adder-based architectures that are optimized for area and delay.
Richard Conway 0001, John S. Nelson
IEEE Trans. Computers2
1999 Fast Converter for 3 Moduli RNS Using New Property of CRT
abstract
This paper presents a new fast RNS converter for the 3 moduli set of the form {2/sup n/-1,2/sup n/,2/sup n/+1}. A new property of the Chinese remainder theorem (CRT) is also presented and this property is used to develop a fast converter for this 3 moduli set. The resulting implementation is based on carry-save adders and one carry-propagate adder stage, without the need for any look-up tables. The new design is faster and smaller than existing designs.
Richard Conway 0001, John S. Nelson
IEEE Trans. Computers2