Designing generalized in-memory computing (IMC) hardware that efficiently supports a variety of workloads requires extensive design space exploration, which is infeasible to perform manually. Optimizing hardware individually for each workload or solely for the largest workload often fails to yield the most efficient generalized solutions. To address this, we propose a joint hardware-workload optimization framework that identifies optimised IMC chip architecture parameters, enabling more efficient, workload-flexible hardware. We show that joint optimization achieves 36%, 36%, 20%, and 69% better energy-latency-area scores for VGG16, ResNet18, AlexNet, and MobileNetV3, respectively, compared to the separate architecture parameters search optimizing for a single largest workload. Additionally, we quantify the performance trade-offs and losses of the resulting generalized IMC hardware compared to workload-specific IMC designs.

Noise in image sensors led to the development of a whole range of denoising filters. A noisy image can become hard to recognize and often require several types of post-processing compensation circuits. This paper proposes an adaptive denoising system implemented using analog in-memory neural computing network. The proposed method can learn new noises and can be integrated into or alone with CMOS image sensors. Three denoising network configurations are implemented, namely, (1) single layer network, (2) convolution network, and (3) fusion network. The single layer network shows the processing time, energy consumption and on-chip area of 3.2$\mu$s, 21n J per image and 0.3mm2respectively, meanwhile, convolution denoising network correspondingly shows 72m s, 236$\mu$J and 0.48mm2. Among all the implemented networks, it is observed that performance metrics SSIM, MSE and PSNR show a maximum improvement of 3.61, 21.7 and 7.7 times respectively.

The selection of hyperparameters and circuit components for optimum hardware implementation of a neural network is a challenging task, which has not been automated yet. This work proposes the method for the selection of optimum neural network architecture and hyperparameters using genetic algorithm based on the hardware-related performance metrics, such an on-chip area, power consumption, processing time and robustness to hardware non-idealities, and focus on memristor-based analog network architecture. The experimental results show that the proposed approach allows to select the optimum architecture based on the designers' preferences.

The volume, veracity, variability, and velocity of data produced from the ever increasing network of sensors connected to Internet pose challenges for power management, scalability, and sustainability of cloud computing infrastructure. Increasing the data processing capability of edge computing devices at lower power requirements can reduce several overheads for cloud computing solutions. This paper provides the review of neuromorphic CMOS-memristive architectures that can be integrated into edge computing devices. We discuss why the neuromorphic architectures are useful for edge devices and show the advantages, drawbacks, and open problems in the field of neuromemristive circuits for edge computing.

The impact of device-to-device, cycle-to-cycle, and parasitic variations in memristor devices on the performance of neural network architectures is not a fully understood topic. In this paper, we present an explicit analysis of memristor variabilities and non-idealities of memristive crossbar based learning architectures. The measurements of real devices and their effects on dot product operation in a memristive crossbar is reported. The effect of these non-idealities, limited resistive levels and variabilities on the performance and reliability of two-layer Artificial Neural Network (ANN), Convolutional Neural Network (CNN) and Binary Neural Network (BNN) is analyzed and presented.

The implementation of backpropagation algorithm using gradient descent operation with analog circuits is an open problem. In this paper, we present the analog learning circuits for realizing backpropagation algorithm for use with neural networks in memristive crossbar arrays. The circuits are simulated in SPICE using TSMC 180nm CMOS process models, and HP memristor models. The gradient descent operations are validated comprehensively using the relevant transfer characteristics and transient response of individual circuit modules.

Hierarchical temporal memory (HTM) is a machine learning algorithm inspired by the information processing mechanisms of the human neocortex and consists of a spatial pooler (SP) and temporal memory (TM). In this paper, we develop circuits and systems to achieve the optimized design of an HTM SP, an HTM TM, and a memristive analog pattern matcher for pattern recognition applications. The HTM SP realizes an optimized hardware design through the introduction of mean overlap calculations and by replacing the threshold determination in the inhibition stage with a weighted summation operator over the neighborhood of the pixel under consideration. HTM TM is based on discrete analog memristive memory arrays and a weight update procedure. The operation of the proposed system is demonstrated for a face recognition problem, using the standard AR, ORL, and Yale databases, and for speech recognition, using the TIMIT database, with achieved accuracies of 87.21% and approximately 90%, respectively, given an SNR of 10 dB. Visual data processing using binary HTM SP features requires less storage and processing memory than required by the traditional processing methods, with the area and power requirements for its implementation being 0.096 mm2and 1756 mW, respectively. The design of the TM circuit for a single pixel requires 23.85 μm2of area and 442.26 μW of power.