CUDA kernels are essential for high-performance computing, yet their deployment has been limited to vendor-specific chips. Unless highly efficient computational kernels are custom-implemented by experts, other chips may face problems such as low utilization and inability to accelerate AI computing. In this paper, we introduce CKTI, a domain-specific compiler that lowers CUDA kernels to Triton-IR, thereby decoupling them from proprietary hardware and fostering diversity across the computing ecosystem. CKTI proposes a scheduling algorithm that transforms the threading model from thread-level to tile-level, along with a mapping scheme from explicit control-structure characteristics to dynamic masks. It also incorporates a custom dialect to express the complete semantics and optimizable properties of the kernel. These collectively ensure performance portability and cross-platform deployment. The results show that CKTI produces correct outputs on different hardware platforms and delivers competitive performance, achieving 1.28X speedup on NVIDIA, 1.17X on AMD, 1.14X on MetaX, and unlocking deployment on Cambricon platforms. Additionally, we validate CKTI’s support for end-to-end workloads across multiple architecture, including NPUs and GPGPUs.

Deep learning compilers optimize DNN program execution by capturing them as operator-based computation graphs. However, developers’ deep learning programs often contain complex Python language features that prevent compilers from recognizing the entire program as a complete computation graph, resulting in sub-optimal performance. Our analysis reveals that actual capture failures involve only a few lines of code, we believe this problem can be addressed through code repair rather than extensive compiler improvements. To address this challenge, we introduce GraphGlue, a multi-agent system that leverages LLMs to repair and optimize DNN programs for compiler requirements, thereby maximizing the performance benefits of deep learning compilers in inference scenarios. GraphGlue employs (1) graph-break cause mining (GCM) to identify hidden causes of computation graph breaks and facilitate LLM-based repair, and (2) self-correction with reject sampling (SRS) to alternate between code debugging and regeneration, effectively avoiding ineffective feedback attempts caused by incorrect initial optimization strategies. Experimental results demonstrate that programs optimized by GraphGlue achieve up to 2.19x (1.23x on average) speedup compared to using TorchDynamo directly, and deliver up to 15.77x (8.74x on average) memory savings compared to state-of-the-art AI compiler frontends. GraphGlue exhibits strong generalization capabilities across 1,411 real-world user programs, successfully optimizing 92.63% of them. Code is available at https://github.com/Jamesswang/GraphGlue.

As the feature size of integrated circuits (ICs) continues to shrink, radiation-induced multiple bit upsets (MBUs) become more frequent than single bit upsets (SBUs) in nanometer ICs. However, it is still very difficult and time consuming to evaluate the sensitivity of digital very large scale ICs (VLSIs) to MBUs. To accelerate MBU evaluation, an MBU emulation platform is proposed via hardware-software co-design approach in this paper. Based on the proposed layout back-annotation technique, the platform back-annotates information of adjacent flip-flop (FF) cells in layout-level physical gate-level (PGL) netlist to the matching register cells in register transfer level (RTL) code, and is able to perform fast and accurate MBU emulation for layout-level digital VLSIs. Finally, several experiments on four different digital designs are implemented with Xilinx Zynq-7000 FPGA, and the correctness and effectiveness of the proposed MBU emulation platform are verified by these experiments.

Word embedding models treat words with equal status, which leads to the neglect of hierarchical semantic relationships between words (e.g., ‘green’ – ‘color’ and ‘cat’ – ‘mammal’). To build a hierarchical structure of words from raw text data, we propose an unsupervised model to learn word hierarchical representations (WHR), which are extended from word representations. Globally, WHRs can describe a word with several other words representing the basic attributes. The WHR model is an extended continuous bag-of-words (CBOW) neural language model with perceptual grouping and attention mechanisms. We further use WHRs to generate document representations, that are more expressive than some widely used document models, such as latent topic and deep learning models. Experimental results demonstrated that our model outperforms state-of-the-art baselines in terms of document retrieval, document classification, and sentiment analysis.