In today’s fast-changing business environment, organizations need to be adaptable and responsive to change. Effective decision-making enables companies to cope with uncertainty and adjust their strategies and operations promptly. In this context, the emergence of intelligent decision support systems (DSS) shows great promise. These systems enable companies to analyze data, identify patterns, and offer valuable insights to facilitate informed decision-making. An intelligent DSS for updating control plans is presented in this paper. The proposed system incorporates two methods to assist the decision-maker in choosing the optimal control scenario. The first involves making a manual decision based on several criteria. The second uses the case-based reasoning (CBR) technique to make an automatic recommendation. Moreover, the suggested recommender system (RS) enables the control plans to be updated regularly depending on the current state of the process quality. To increase the quality of decisions, CBR is used to acquire the necessary knowledge. The viability and applicability of the suggested RS are demonstrated through a practical case study.

This paper revolves around a test of a reconfigurable hardware system based on sequential logic (abbreviated, RHSS). The latter is a sequential hardware device that allows to change the hardware resources at run-time in order to modify the system functions and therefore to dynamically adapt the system to its environment. In order to reduce time and effort for finding test patterns and analyzing a circuit for its faults, we endeavor to show the way inter-circuits fault collapsing for RHS based on combinational logic remains valid and can be extended to RHSS. The application of the inter-circuits technique reduces the number of faults dealt with by eliminating redundant faults existing between circuits composing the RHSS. For a scalable RHSS, it is often impractical to reach an overall fault coverage. We propose two test techniques that target a minimal necessary set of faults while ensuring an acceptable fault coverage that answers the manufacturer requirements. For so doing, we promote a guiding method for rating potential faults in terms of their occurrence and severity where a fault is weighted according to how serious its consequence and how frequent it can occur. The proposed approach is implemented in a new version of the original TnTest tool.

This paper deals with the test of a reconfigurable hardware system (RHS). The latter is a hardware device that allows to change the hardware resources at runtime in order to modify the system functions and therefore to dynamically adapt the system to its environment. The increasing functional complexity of embedded systems and the transition to the RHS make the hardware testing a challenging task, especially under the confine of providing a high quality with a low cost. Considering the fact that the hardware test represents a key cost factor in a production process, an optimal test strategy can be advantageous in the competitive industrial market. Accordingly, this paper introduces a new methodology for an efficient hardware test of RHS. For an RHS, the number of stuck-at faults can be very large, which leads to a significant slowdown in the testing process. Because of the redundancy of faults between the different circuits composing an RHS, the proposed methodology aims at minimizing the number of faults using the inter-circuits relationships and consequently at providing an optimal fault set that can be effectively used for testing. Efficient techniques for test generation and test set validation are proposed to provide the test patterns for faults reduced by inter-circuits fault collapsing. The application of the generated test patterns is typically sufficient to provide an overall fault coverage. The proposed methodology is implemented in a new visual environment named TnTest. An experimental study confirms and validates the expected findings. Note to Practitioners-This paper addresses possible challenges for future generations of adaptive embedded systems. It proposes an original methodology for an efficient reconfigurable hardware system (RHS) hardware test. The main objective is to significantly reduce time and cost needed for the testing process. For an RHS, the number of stuck-at faults can be very large, which can cause a major slowdown in the hardware test. Based on the inter-circuits relations existing between the different circuits composing an RHS, the proposed methodology decreases considerably not only the number of the faults but also the test patterns needed for testing. The application of the generated test patterns is typically sufficient to provide an overall fault coverage. The proposed methodology is implemented in a new visual software environment named TnTest, which is capable of providing the smallest fault set as well as the efficient test set that can be effectively used for testing. This environment can be applied to test any embedded device that can be deployed in any new application based on flexible technologies. It can also be useful in manufacturing industries for a required improvement of the production process in relation to time and cost.