Maximal distance binary codes that are composed of individual characters from the residues of pairwise prime polynomials are constructed and compared to Reed-Solomon codes. Although these binary residue codes are not as efficient as R-S codes in that codeword lengths are shorter, error decoding involves only binary and not finite field operations and thus allows faster decoding and greater data rates. Data rates of hundreds of megabits per second are feasible if decoding is implemented with VLSI array logic. Constructions of array logic for use in decoding are described. These codes lend themselves for use in a concatenated coding scheme.

It is shown that if a machine M con be mapped into a simpler machine M' by a homomorphism, then an error correcting/detecting code can be applied to the states of M such that the parity check bits are generated independently of the information bits that form the state assignment of M. If such a homomorphism does not exist, it is shown how to produce one by altering M if M consists entirely of loops as is the case with a digital computer. The method presented here is a generalization to sequential machines of the separate adder and checker concept used for checking addition. Methods of coding are given. Application to computers is given.

It is shown how single-error correction in a residue arithmetic system can be accomplished in an efficient and fast manner. Two redundant moduli are necessary. This construction is extended to multiple errors. Another method of error detection or correction for residue arithmetic is also described. Implementation of these methods is considered. An example of the single-error correction procedure is given.

It is shown how index registers can be made so as to act parallel to the computer instruction flow, thus not requiring a programmed instruction to decrement (or increment) and jump. This method would save one instruction per loop but would require more hardware.

This paper compares the properties of infinitely recurring sequences and terminating sequences generated by arithmetic division with the properties of linear feedback shift registers. The concept of state is defined as equivalent to the remainder or residue in a division process. It is shown that such state graphs have forms identical with those of classes of feedback shift registers. Divisors generating classes of cycles and trees are determined. Sums of such graphs are analyzed. Applications of such arithmetic sequences may be those where feedback shift registers are used. If computers are available, no extra hardware is needed.