Early detection of obstructive sleep apnea (OSA) is extremely necessary to control its’ rising prevalence worldwide. Conventional diagnostic method like polysomnography (PSG) is uncomfortable, intrusive, and costly, thus, limiting its’ easy accessibility among people. To address this, we propose a novel deep learning method for detecting OSA using photoplethysmography (PPG) signal, a non-invasive method that is commonly available in wearable devices. We introduce a novel methodology using Multivariate Long Short-Term Memory-Fully Convolutional Network (MLSTM-FCN) model that effectively captures both temporal dependencies and local features in PPG signals for OSA detection. A new windowing technique was introduced to ensure apneic events are centered within each window to enhance the model’s ability to detect delayed physiological responses to apnea. The model was trained and evaluated on the Multi-Ethnic Study of Atherosclerosis (MESA) dataset, achieving an improvement of 11.3% in accuracy over the state-of-the-art method. The method obtained an accuracy of 93.44%, precision of 0.94, recall of 0.91, and an F1-score of 0.93. These results demonstrate the potential of our method in accurately identifying OSA events. This method offers a unobtrusive, comfortable, and cost-effective alternative to traditional diagnostic tools, making it suitable for long-term, home-based monitoring.

Obstructive sleep apnea (OSA) has become a serious health concern with increasing morbidity worldwide. Even though polysomnography is widely used by physicians for diagnosing OSA, the process is costly, time-consuming, and uncomfortable for patients. This increases the demand for developing unobtrusive, cost-effective, and reliable solutions for detecting OSA and reducing patient discomfort. Several machine learning-based and some deep learning based methods using extracted ECG features for OSA detection from ECG are found to be less reliable due to the manual feature extraction process, very few studies(included in the comparison table of below section) have used only deep learning methods for OSA detection from ECG signals. In this study, we proposed a novel deep learning method that leverages convolutional neural networks (CNN) and long short-term memory (LSTM) networks to learn spatial and temporal features for detecting OSA from ECG data. Our model was trained and evaluated on the publicly available MESA and Apnea-ECG datasets to assess its robustness. In a prudent data windowing step, we center the apnea data within each data window, enabling the model to better learn apnea patterns and resulting in achieving an accuracy of 95.4%, 92.2%, Specificity of 95.1%, 92.8%, Sensitivity of 94.8%, 91.6% and F1 score of 94.1%, 92.1% respectively on MESA and Apnea-ECG dataset. Our model yields an increase of 0.57% and 9.31% in specificity, 1.87% and 50.47% in sensitivity, 4.89% in F1-score, and 3.47% and 17.77% in accuracy against the best result we found using the Apnea-ECG and MESA dataset respectively. The results show our proposed model outperforms state-of-the-art methods on the MESA dataset and achieves equally good results on the Apnea-ECG dataset. Implementation of our model on Jetson orin AGX board gains comparable results with the above-stated accuracy showing the possible practical use of our methodology. These findings highlight the model’s stability, robustness, and high accuracy in detecting OSA.

Field-Programmable Gate Arrays (FPGAs) are extensively utilized in various fields due to their inherent flexibility and ability to be reconfigured. The functionality of digital designs within FPGAs is stored as configuration frames within the bitstream. Previous studies introduced tools like BIL, RapidSmith, Debit, DAT and BitFREE, which reverse-engineer the bitstream to reveal the Boolean logic of Look-Up Tables (LUTs) using the Xilinx ISE design suite. This tool produces both the bitstream and a textual representation of the placed design in the form of the Xilinx Design Language (XDL) file, enabling deeper insights into the FPGA’s internal structure. However, with the introduction of the AMD Xilinx Vivado design suite, support for XDL and text-based hardware adjustments discontinued, making it more challenging to reverse-engineer modern bitstreams. Our prior study, REVBiT, utilized the AMD Xilinx Vivado Design Suite, which extracted the LUTs and identified Boolean logic but failed to identify the pin combination in its present form. The pin combination of LUTs is also essential information for determining the correct configuration of LUTs in the bitstream. To address the limitation of state-of-the-art methods, we introduce REVBiT 2.0, a methodology for extracting LUTs and their Boolean logic, along with the pins connection of the LUT. Our proposed deep-learning models have been trained and tested with 92,82,950 data samples for the pin combination and Boolean logic identification. The experiment for bitstream extraction is carried out on a real FPGA board with the help of a logic analyzer. Our proposed methodology has been experimentally validated on AMD Xilinx 7-Series, Ultrascale, and Ultrascale+ FPGA device families for 2, 3, and 4-input LUTs using the AMD Xilinx Vivado design suite and relying on bitstream without any additional information. We achieved ≈ 100% accuracy for the LUT extraction, more than 87.50% prediction accuracy for pin combination and 92.43% for Boolean logic identification from the bitstream.

The interpretability of machine learning model is crucial in healthcare as it fosters reliability and supports clinicians in making informed decisions based on predictions. However, recent approaches for vital parameter estimation often act as black boxes, lacking clarity in their predictive reasoning. Therefore, accurate estimation of vital parameters is crucial not only for timely diagnosis and effective patient monitoring but also for ensuring that clinicians can trust and understand the model’s predictions. In this study, we introduce XVPE-Net, an explainable framework aimed at improving the state-of-the-art VPE-Net model for estimating vital parameters: heart rate (HR), respiratory rate (RR), systolic blood pressure (SBP), and diastolic blood pressure (DBP). Our model enhances interpretability by visually highlighting key parts of the PPG signal that significantly influence VPE-Net’s predictions of vital parameters. We test our model using 1,000 PPG segments from 38 subjects in the MIMIC-III dataset, which is available in the Physionet repository. The results show strong predictive capabilities, along with better transparency and reliability. This study helps us understand how the model makes decisions and supports the use of explainable AI in health monitoring, contributing to the development of more reliable models for medical applications.

Age prediction for integrated circuits (ICs) is essential in establishing prevention and mitigation steps to avoid unexpected circuit failures in the field. Any electronic system would get benefit from an accurate age calculation. Additionally, it would assist in reducing the amount of electronic waste and the effort toward green computing. In this article, we propose a methodology to estimate the age of ICs using the Gaussian process regression (GPR). The output frequency of the ring oscillator (RO) is influenced by various factors, including the trackable path, voltage, temperature, and ageing. These dependencies are leveraged in the GPR model training. We demonstrate the RO’s frequency degradation by employing the Synopsys HSPICE tool with 32 nm predictive technology model (PTM) and the Synopsys technology library. We used temperature variation from 0 °C to 100 °C and voltage variation from 0.80 to 1.05 V for the data acquisition. Our methodology predicts age precisely; the minimum prediction accuracy with a month deviation on linear sampling rate is 85.36% for 13-Stage RO and 87.09% for 21-Stage RO, with a range of improvement in prediction accuracy compared to state-of-the-art (SOTA) is 9.74% to 16.99%. Similarly, on the logarithmic sampling rate, the prediction accuracy for 13-Stage RO and 21-Stage RO are 98.62% and 98.56%, respectively. The proposed methodology performs more accurately in terms of prediction accuracy and age prediction deviation from the SOTA methodology.

This paper proposes GRIPT, a novel graph attention-based inductive methodology that enables a fast and accurate average power estimation of synthesized ASIC Design from RTL simulation, bypassing gate-level simulation. The proposed GRIPT methodology with features-aided attention mechanism-based inductive Graph Neural Network (GNN) model propagates the input wires’ toggle rates acquired from the RTL SAIF file through the circuit. We examine the proposed GRIPT methodology’s versatility by testing circuits across technology nodes and foundries like TSMC 65nm, 40nm, 90nm, 130nm and GF 40nm while training exclusively on the TSMC 65nm technology node. We introduce unseen and untrained logic cells to test the transferability of the proposed GRIPT model in toggle rate prediction across technology nodes. We evaluate the scalability of the proposed GRIPT by testing circuits of considerable size, like circuit trigonometry from OpenCores, and circuits arbiter, multiplier, div, log2, sin, square and sqrt from the EPFL benchmark suite, without training them. The proposed GRIPT surpasses the state-of-the-art GRANNITE model in predicting the unseen and untrained logic cell’s toggle rates to justify the proposed GRIPT’s transferability for designs across technology nodes to achieve an average improvement of 6.74%, 5.53%, 8.93%, 6.88% and 7.22%, respectively. To demonstrate versatility and scalability, the proposed GRIPT methodology outperforms the commercial RTL power estimation tool and GRANNITE in estimating the average power of circuits spanning TSMC 65nm, 40nm, 90nm, 130nm, and GF 40nm technology nodes, with a mean improvement of 23.42%, 16.59%, 16.35%, 27.16%, and 28.87%; 2.01%, 0.97%, 0.98%, 1.6% and 2.72%, respectively. The proposed GRIPT is 12.57X and 1.1X faster, with an average inference throughput (number of cycles inferred per second) of 1384.6 Hz compared to the commercial gate-level power estimation tool and GRANNITE, respectively.

This paper proposes an inductive Graph Neural Network (GNN) based methodology for accurate and fast average power estimation of logic-synthesized and RTL-simulated ASIC Design, eliminating gate-level simulation. With the novel variation of inductive GNN architecture, the proposed model propagates the input wires’ toggle rates acquired from RTL simulation through the synthesized design. We only train the proposed model on circuits synthesized from TSMC 65nm technology node but test on the circuits synthesized across TSMC 65nm, 40nm, 90nm, 130nm and GF 40nm technology nodes. We test the inductivity of the proposed model to predict the output wires’ toggle rates of unseen and untrained logic cells of the designs. We compute the proposed methodology’s average power inference throughput (number of cycles inferred per second) for speed comparison. The proposed model does better than state-of-the-art architecture GRANNITE to predict the unseen and untrained logic cell’s toggle rates of the designs across TSMC 65nm, 40nm, 90nm, 130nm, and GF 40nm technology nodes, showing an average improvement of 6.67%, 8.49%, 9.26%, 7.47% and 6.36%, respectively. The proposed methodology is more accurate than the commercial RTL average power estimation tool and GRANNITE in estimating the average power of circuits across TSMC 65nm, 40nm, 90nm, 130nm, and GF 40nm technology nodes by achieving a mean improvement of 24.94%, 16.77%, 17.65%, 29.72%, and 32.84%; 2.75%, 1.1%, 1.81%, 2.59% and 4.49%; respectively. The proposed methodology is 11.07X faster, with an average inference throughput of 1.218kHz, than the commercial gate-level average power estimation tool.

In physical design, back-end flow, clock tree synthesis, and routing steps are vital in design optimization. Early and accurate QoR parameter prediction is paramount for design optimization and timely design delivery. In this paper, we propose an accurate and fast post-route QoR data prediction methodology by skipping CTS and Routing steps from the physical design back-end flow. This proposed methodology focuses on database generation and prediction of 26 QoR report parameters of post-Route QoR report. In this methodology, we are considering nine benchmark circuits from ISCAS89, IWLS 2005, and ISPD 2013. We use the random split method to split 50% of the data for training and the remaining 50% for testing purposes. We are validating our proposed method for two different technology nodes, i.e., TSMC 40nm and TSMC 65nm, which ensure robustness and reusability of the proposed methodology. Experimental results show that the average mean square error for all the parameters for both technologies is 10-2, while most of the parameter MSE is in the range of 10-4to 10-6for both technology nodes. It is also shown that the accuracy significantly improved (95% in TSMC 40nm and 98% in TSMC 65nm) and is comparable to the other work, along with the advantage of skipping CTS and Route both steps. Skipping of CTS and Routing optimizations and use of the artificial neural network (ANN) makes the proposed method a fast method as ANN is a less weighted network.

Cardiovascular diseases (CVDs) are the major cause of global morbidity and mortality. CVDs can be preliminarily diagnosed by analyzing a patient’s electrocardiogram (ECG), which requires long-term continuous ECG monitoring to suitably detect the onset of the disease. However, ECG data acquisition involves multiple lead attachments and requires regular intervention by an expert, thereby making the process cumbersome and inappropriate for continuous health monitoring due to limited portability and discomfort caused to the patients. Nowadays, automated ECG measurement techniques are gaining popularity in wearable health monitoring applications to seamlessly identify cardiac abnormalities even in a home environment. On the other hand, photoplethysmography (PPG) signals can be acquired from the wrist or fingertip of a patient by using a lead-less patch-less set-up that can be easily integrated with smart wearable devices. Therefore, to address the aforementioned demerits associated with ECG devices, a few researchers have fostered the idea of reconstructing ECG from photoplethysmogram (PPG) signals to generate simple yet effective CVD monitoring methodologies. Hence, in this paper, we propose P2E-LGAN, a hybrid generative adversarial network (GAN) based framework for generating ECG from PPG. The proposed network is evaluated on a benchmark database combined with ECG and PPG data. The inclusion of LSTM in the GAN network reduces the root mean square (RMSE), mean absolute error of heart rate (MAE(HR)) and percentage root mean square difference (PRD) by 35.7%, 37.2% and 9.8% respectively. Individual graphical analysis and performance evaluation of different metrics with state-of-the-art methods demonstrate the effectiveness of the proposed framework for reconstructing ECG from PPG.

Field-Programmable Gate Arrays (FPGAs) are widely used in various applications due to their flexibility and reconfigurability, and they store the functionality of digital design in the form of configuration frames within the bitstream. In the earlier studies, state-of-art methodologies, such as BIL and RapidSmith reverse engineer the bitstream to identify the boolean logic of LUTs using the Xilinx ISE tool, which provides bitstream and textual information of placed design in the form of a Xilinx Design Language (XDL) file. However, the more recent tool, Xilinx Vivado, does not include XDL support or text-based hardware adjustments. To resolve the above problem, here we introduce a methodology called REVBiT for LUT extraction and boolean logic identification that offers the potential to verify functionality against a trusted reference or rectify corrupted bitstream data by correcting it. Also, our propose methodology verified on AMD Xilinx 7-Series, Ultrascale and Ultrascale+ device families FPGAs using the Xilinx Vivado tool and does not rely on additional information besides the bitstream. We achieved 100% accuracy for the LUT extraction and 93.86%, 96.26%, and 95.16% accuracy for the boolean function identification for 7-Series, Ultrascale and Ultrascale+ device families, respectively.

In this paper, we propose GRASPE, a graph representation learning-based methodology to accurately estimate post-synthesis average power consumption from the RTL to expedite the time to market in the ASIC design. Our proposed methodology uses novel graph neural network architecture (GNN) to work on unoptimized and unmapped post-translated netlist files. The GRASPE learns to propagate the average toggle rates with embedded feature values as vectors on each logic cell during training and then predicts the average toggle rates of a new design during testing. We attain a mean improvement of 19.84% and 4.42% in average toggle rates prediction, 14.12% and 2.67% in average power estimation over the commercial RTL power estimation tool and Graph Convolutional Network as GNN, respectively and 17.96X faster than the commercial gate-level power estimation tool. Subsequently, we evaluate GRASPE with the state-of-the-art GRANNITE for inference latency and average power estimation and demonstrate an average improvement of 3.985X and 1.28%, respectively.

Logic locking is one of the most promising design-for-trust technique for protecting intellectual property from reverse engineering, IP piracy, and modification throughout the electronic supply chain. However, oracle-less deobfuscation attacks that do not require an activated chip have been successful in obtaining the secret key of locked designs. This requires a detailed determination of the extent of vulnerability available in obfuscated circuitry. In this paper, we propose the oracle-less DeepAttack: an attack on logic locking that is capable of extracting the activation key of the locked netlist using a deep learning model. Based on the ISCAS-85 and EPFL benchmarks evaluation, DeepAttack achieves an average key prediction accuracy of 93.39%, outperforming the oracle-less state-of-the-art attacks SAIL, SnapShot, and OMLA by 21.28, 10.73, and 3.84 percentage points, respectively.

In this paper, we propose two models to predict 26 parameters data of post clock tree synthesis (post-CTS) quality of results (QoR) report without running the CTS optimization step. In model 1, we considered 9 benchmark circuits (6 from ISCAS89 and 3 from open cores). We randomly split 50% of the total data into the training sample and the other 50% in the testing sample. In model 2, we use 6 benchmark circuit data for training purposes and use 3 benchmark circuit data for testing purposes which are unseen to the model. We utilize a regression neural network for predictions. To ensure robustness and reusability of the proposal, we validate our proposed models for two different technology nodes i.e. TSMC 65nm and TSMC 90nm. Experimental results show that the average mean square error for all the parameters for both the technologies is of the order of 10-3while most of the parameter MSE is in the range of 10-5to 10-7for both the technology nodes. These data ensure robustness and re-usability of the proposal with a high level of accuracy.