The development of small DNA sequencers offers a transformative opportunity for portable genomics. However, current systems lack integrated bioinformatics computing and instead rely on bulky external systems. To address this limitation, we propose an embedded System-on-Chip (SoC) architecture aimed at mobile DNA sequencing applications, representing an initial step towards a fully integrated bioinformatics solution. The proposed heterogeneous SoC leverages the open-source RISC-V architecture and incorporates two specialized bioinformatics accelerators: one for deep learning-based basecalling and the other for sequence alignment. An FPGA-realized basecalling accelerator achieves a nearly 2000× speedup over a standalone RISC-V core and demonstrates 11.5× and 1.2× higher energy efficiency than x86 CPUs and high-end GPUs, respectively, while maintaining an accuracy rate of 83.7%. A separate accelerator optimized for sequence comparison, offers 538× and 357× performance-per-joule boost relative to x86 CPUs and an existing state-of-the-art accelerator, respectively, while far exceeding other platforms. A preliminary ASIC prototype operates at 250 MHz with a power consumption of 34 mW, demonstrating significant potential for the proposed approach. Overall, the proposed SoC architecture presents a compelling first step towards embedded bioinformatics hardware for mobile DNA sequencing.

DNA sequencers are being miniaturized and increasingly targeted toward mobile applications. However, the intense bioinformatic computing needs of sequencers present a challenge for remote use with limited energy supply. This article presents a step toward realizing a low-power and high-speed bioinformatic engine, a hardware-accelerated basecaller, for mobile sequencing applications. The design is targeted for nanopore-based sequencers and is architected to easily scale to the complexity of this sensor. In addition to accelerating the CPU in real time with a custom field-programmable gate array (FPGA) through a high-speed serial link, the proposed framework envisages the challenging memory requirement of high-order nanopore sensors. The framework proposes a memory management scheme, which provisions the memory requirement problem in three dimensions: the basecalling speed, the circuit's area, and power consumption. The implementation results demonstrate a $142\times $ basecalling speed improvement over a 12-core CPU-only reference, as well as significant speedup compared with other existing solutions. Also, an energy efficiency improvement of three orders of magnitude is measured.

Energy-efficient communications have become one fundamental aspect for today's cutting-edge wireless technologies due to its valuable impact on the environment. In this paper, we augment our earlier study for the user equipment's (UE) energy efficiency (EE) in the long-term evolution (LTE) downlink by looking at real-time heterogeneous traffic QoS requirements. In particular, we utilize the previously proposed cloud radio access network (C-RAN) and ray tracing (RT)-based scheduling model to optimize both of the EE and the packet delay jitter for real-time applications with fixed packet delay budget subject to other traffic types requirements. Using the utility-based scheduling approach, we formulate the resource allocation problem as a weighted sum binary integer programming (BIP) problem. Due to the inherent complexity of the problem formulation which hinders finding its solution directly, four heuristic algorithms are proposed to solve the optimization problem. Numerical simulations are conducted on three different traffic types each belonging to one of the popular QoS classes; best-effort class, rate, and delay-constrained classes. The obtained results demonstrate a substantial improvement in the system's performance achieved by our proposed schemes compared to other existing schemes.

The term Energy Efficiency (EE) is turning out to be a radical characteristic for today's 4G networks - which provide energy-hungry wireless services - especially from the battery-limited devices' perspective. In addition to the EE, meeting firm levels for the quality-of-service (QoS) of those energy demanding applications is inevitable. In this paper we study the EE of the user equipment (UE) in the LTE downlink and the delay jitter as a fundamental QoS metric for various real-time applications. The study focuses mainly on the Voice over LTE (VoLTE) traffic as being a heavily used service. We provide a multiobjective optimization for both the EE and the delay jitter subject to fixed delay budget. To address the complexity of the proposed optimal scheduler, two different heuristic algorithms were developed. Numerical results demonstrate that our proposed schedulers achieve better trade-off for the EE versus the delay jitter compared to existing state-of-the-art schedulers.

In this paper, we first present a detailed analysis for studying the effect of changing the time difference between two successive channel predictions on the outage probability and the system's reliable transmission rate. Secondly, we propose a low complexity heuristic scheduling algorithm that utilizes long-term ray tracing channel predictions to improve the system throughput in wireless networks. The proposed heuristic algorithm achieves almost identical throughput as the optimal scheduler and outperforms traditional channel-aware schedulers in terms of system's average throughput with low computational cost. The scheduler's performance is tested in the presence of Rayleigh fading and log-normal shadowing effects.