Spiking Neural Networks (SNNs) offer inherent advantages for low-power inference through sparse, event-driven computation. However, the theoretical energy benefits of SNNs are often decoupled from real-world hardware performance due to the opaque relationship between training-time choices and inference-time sparsity. While prior work has focused on weight pruning and model compression, the role of training hyperparameters—specifically surrogate gradient functions and neuron model configurations—in shaping hardware-level activation sparsity remains underexplored. This paper presents a comprehensive workload characterization study quantifying the sensitivity of hardware latency to SNN hyperparameters. We decouple the impact of surrogate gradient functions (e.g., Fast Sigmoid, Spike Rate Escape) and neuron models (LIF, Lapicque) on classification accuracy and inference efficiency across three event-based vision datasets: DVS128-Gesture, N-MNIST, and DVS-CIFAR10. Our analysis reveals that standard accuracy metrics are poor predictors of hardware efficiency. For instance, while Fast Sigmoid achieves the highest accuracy on DVS-CIFAR10, the Spike Rate Escape reduces inference latency by up to $\mathbf{1 2. 2 \%}$ on DVS128-Gesture with minimal accuracy trade-offs. Furthermore, we demonstrate that neuron model selection is as critical as parameter tuning; transitioning from LIF to Lapicque neurons yields up to a $28 \%$ latency reduction. We validate our analysis on a custom cycle-accurate FPGA-based SNN instrumentation platform, and our characterization demonstrates that sparsity-aware hyperparameter selection can improve accuracy by $9.1 \%$ and latency by over $2 \times$ compared to baselines. These findings establish a methodology for predicting hardware behavior from training parameters, motivating the inclusion of sparsity-sensitivity in future SNN performance analysis. The RTL code and other reproducibility artifacts are available at https://zenodo.org/records/18893738.

Spiking Neural Networks (SNNs) offer potential advantages in energy efficiency but currently trail Artificial Neural Networks (ANNs) in versatility, largely due to challenges in efficient input encoding. Recent work shows that direct coding achieves superior accuracy with fewer timesteps than traditional rate coding. However, there is a lack of specialized hardware to fully exploit the potential of direct-coded SNNs, especially their mix of dense and sparse layers. This work proposes the first hybrid inference architecture for direct-coded SNNs. The proposed hardware architecture comprises a dense core to efficiently process the input layer and sparse cores optimized for event-driven spiking convolutions. Furthermore, for the first time, we investigate and quantify the quantization effect on sparsity. Our experiments on two variations of the VGG9 network and implemented on a Xilinx Virtex UltraScale+ FPGA (Field-Programmable Gate Array) reveal two novel findings. Firstly, quantization increases the network sparsity by up to 15.2% with minimal loss of accuracy. Combined with the inherent low power benefits, this leads to a 3.4× improvement in energy compared to the full-precision version. Secondly, direct coding outperforms rate coding, achieving a 10% improvement in accuracy and consuming 26.4× less energy per image. Overall, our accelerator1achieves 51 × higher throughput and consumes half the power compared to previous work.

This paper extends the concept of using dynamic braking resistors (DBRs) in series with the stator of doubly-fed induction generators (DFIGs) to improve low-voltage ride-through (LVRT) performance, specifically under asymmetrical grid faults. Although previous studies have demonstrated the effectiveness of fixed or discrete-valued DBRs in mitigating electrical transients, mechanical issues such as torque loss remain mostly underexplored. In this work, we leverage independent control of the resistance in each stator phase by means of pulse-width modulation to maintain generator torque and cancel the negative sequence component of the grid voltage. By shaping the DBR voltage drop through asymmetric resistances, the resulting negative sequence voltage opposes that of the grid, reducing torque oscillations and enabling more stable DFIG operation during unbalanced faults. Analytical derivations and simulation results validate the proposed control strategy.

Electrical dimensioning design in a railway infrastructure has high complexity and is strongly nonlinear. There are several parameters and constraints to take into account. The presented methodology is working to improve the decision making about the design, hence developing an expert system. The final set of possible solutions that the method is achieved is based on a pair of main objectives. On the one hand are installation costs, environmental impact, main electrical components costs such as catenary, traction substations, neutral zones, and the difficulty to connect substation to general electric grid. On the other hand are exploitation costs, such as maintenance costs and energy loss depending on the dimensioning design. A specific line discretization has been developed in order to distribute the critical zones along the line. Integration of a multiobjective genetic algorithm (NSGA-II), hence the code of the genotype, is another highlight. Electrical analysis, railway systems using single alternate current (1 × 25), and a simplification due to the search of the highest peaks of power demanded by the trains during simulations help to minimize the quantity of studies. Every simulation is possible by using a railway simulator, Hamlet, which provides modules such as infrastructure, rolling stock, signaling, and electrical. Designers have the possibility to analyze several scenarios with different railway exploitation critical levels, analyze electrical degraded situations, and finally obtain an optimal Pareto Front, reaching a powerful methodology to help in the electrical dimensioning design.