This paper presents a scalable hybrid architecture for high performance data-parallel applications on tightly coupled shared-memory CPU-FPGA systems such as the Xilinx Zynq SoC. The aims of the proposed architecture are: 1)to simplify the development of hardware acceleration for dataparallel applications; 2)to reach the performance limit caused by memory access and/or hardware resource available on an FPGA; 3)to reduce the overhead caused by task scheduling and device drivers. The proposed architecture can be used as a generic template to implement data-parallel applications. Each task in an application is mapped to one hardware accelerator, which is called “kernel”. Several identical instances of each hardware kernel execute concurrently to provide parallelism. By deploying the maximum number of instances of the hardware kernel, we make full use of the bandwidth of memory access and the resources available on the FPGA. In order to improve performance further, task scheduling and device drivers are implemented as a hardware scheduler called DmaScheduler on FPGA hardware. Experimental results show 2.93x-51.25x speedup on Zynq FPGA for applications of image processing, Black Scholes option pricing, matrix multiplication and clustering algorithm, compared with existing FPGA implementations.

In this demonstration, we develop a moving object extraction and classification system based on a heterogeneous acceleration platform that consists of a local Zynq terminal and FPGA clusters on the IBM SuperVessel cloud. Extraction of the moving object from the streaming video input is offloaded to the Zynq terminal, while the classification is executed on the cloud. FPGA high level synthesis and Xilinx SDSoC Environment are applied to develop the extraction part of the system. In evaluation, the extraction and classification parts of our system achieve performance of 30 fps and 1 fps respectively for 1080P streaming video input. This demonstration displays a feasible framework for the hardware acceleration of computer vision applications and a possible job division between the terminal and the cloud.

This paper proposes UniStream, a unified stream architecture based on point-to-point stream channels combining both bitstream configuration and data stream processing. In addition, unified APIs are provided to support bitstream configuration and data stream processing, as well as the stream interconnect. A cost model is also presented for the overhead on the stream interconnect, hardware task configuration and data stream processing at system level, which can be used during the early stage of development. The flexibility and high efficiency of UniStream are demonstrated on Xilinx Virtex-5 and Virtex-6 FPGAs. Experimental results on bitstream configuration/ read-back, data encryption/decryption and Discrete Cosine Transformation show that performance can be significantly improved with different stream modes.

Due to the technology scaling, the reconfigurable SoCs built on SRAM-based FPGAs become more susceptible to radiation and aging effects. This paper proposes an adaptive cross-layer fault recovery solution based on hardware/software co-design for reconfigurable SoCs. By pyramidal structure design and cross-layer adaptivity, our solution gives both consideration to hardware circuit integrity at the hardware level and application operating normality at the software level with reduced correction cost. The experiment result shows that the proposed solution can efficiently increase the system reliability and decrease the correction cost.