Demo Data from VLDB 2026 / reviewers in the wild / expert
James H. Shelly
dblp:17/10968
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 1983
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 93% Integrated circuit design · 7% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test › timing verification
statistical timing verification |
0.0 | 1 | 1983 | Statistical techniques of timing verification · DAC 1983 |
Electronic design automation › hardware verification and test
timing verification |
0.0 | 1 | 1983 | Statistical techniques of timing verification · DAC 1983 |
Integrated circuit design
asynchronous circuit design |
0.0 | 1 | 1970 | R70-37 Extensions of Asynchronous Circuits and the Delay Problem I. Good Extensions and the Delay Problem of the First Kind · IEEE Trans. Computers 1970 |
Electronic design automation › design methodology
latency-insensitive design |
0.0 | 1 | 1970 | R70-37 Extensions of Asynchronous Circuits and the Delay Problem I. Good Extensions and the Delay Problem of the First Kind · IEEE Trans. Computers 1970 |
Methods — techniques the papers use, named apart from their topics
statistical analysis · 0.0asynchronous circuit theory · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1983 | Statistical techniques of timing verification
James H. Shelly, David R. Tryon |
DAC | 1 |
| 1970 | R70-37 Extensions of Asynchronous Circuits and the Delay Problem I. Good Extensions and the Delay Problem of the First KindabstractThe author uses the Muller-Bartky asynchronous circuit theory to study the problem of designing circuits whose physical implementations operate correctly despite unpredictable signal delays in the wires connecting the elements. James H. Shelly |
IEEE Trans. Computers | 1 |