Statistical analysis is generally seen as the next EDA technology for timing and power sign-off. Research into this field has seen significant activity started about five years ago. Recently, interest appears to have fallen off somewhat. Also, while a lot of focus has been put on research fundamentals, extremely few applications in industry have been reported so far. Therefore, a group including Infineon Technologies as a leading semiconductor IDM and various universities and research institutes, as well as an EDA provider has tackled key challenges to enable statistical design in industry in a publicly funded project called ldquoSigma65rdquo. Sigma65 strives to provide key foundations to allow a change from traditional deterministic design methods to future design methods driven by statistical considerations. The project starts with statistical modeling and optimization of library components and ranges to statistical techniques for designing ICs on gate level and higher levels. In this paper, we present some results of this project, demonstrating how the interaction between industrial perspective, research institutions and EDA provider enables solutions which are applicable already in the near future. After an overview of the industrial perspective of the current situation in dealing with variations recent results on both statistical timing and power analysis will be given. In addition, recent research advances on fast yield estimation concerning parametric timing yield will be given.

The concepts of design for manufacturability and design for yield DFM/DFY are bringing together domains that co-existed mostly separated until now $circuit design, physical design and manufacturing process. New requirements like SoC, mixed analog/digital design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. For technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. Redesigns and, therefore, respins of the whole development and manufacturing chain lead to high costs of multiple manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels - both for digital as well as for analog - is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (on chip variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to design individual blocks with high robustness (>6sigma). For abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. For the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices

A unified approach to fault simulation for FGDs is introduced. Instead of a direct fault simulation, the proposed approach calculates indirectly from the simulator output the sets of undetectable values of the trapped charge on the floating gate transistor It covers all potential gate charges of an FGD at one or more transistors and allows the application of conventional circuit simulators for simulating DC, AC and transient test. Based on this fault simulation, a test design methodology is presented that can determine all test sets that detect all FGDs for all possible values of gate charge.

In this paper a method for nominal design of analog integrated circuits is presented that includes process variations and operating ranges by worst-case parameter sets. These sets are calculated adaptively during the sizing process based on sensitivity analyses. The method leads to robust designs with high parametric yield, while being much more efficient than design centering methods.

We present a new method for mismatch analysis and automatic yield optimization of analog integrated circuits with respect to global, local and operational tolerances. Effectiveness and efficiency of yield estimation and optimization are guaranteed by consideration of feasibility regions and by performance linearization at worst-case points. The proposed methods were successfully applied to two example circuits for an industrial fabrication process. 1.

In this paper, we present a novel approach to use test stimuli generated by digital components of a mixed-signal circuit for testing its analog components. A wavelet transform is applied to the response signal of the device under test (DUT). We show, that in comparison to Fourier transform or no transform at all, particular properties of this transformation are advantageous for mixed-signal test and especially built-in self test. We introduce a new method for test measurement selection based on a non-deterministic parametric fault model for analog circuits. This approach allows for noise and measurement error in testing. We show, how test quality can be optimized in the presented fault model. Our test methodology is demonstrated on an analog CMOS bandpass filter.