Blockchain technology is very popular nowadays as it ensures decentralization, transparency, and immutability. However, despite its inherent security features, blockchain-based systems have been frequently targeted by adversaries, raising concerns about their trustworthiness. This paper presents a comprehensive study of 24 major attacks against blockchain systems, categorized in a structured, layer-based approach. The study systematically examines the feasibility, underlying incentives, and underlying vulnerabilities exploited in these attacks. We categorize attacks across four blockchain layers, namely the Network, Consensus, Application, and Meta-Application layers, illustrating the diverse nature of security threats. Furthermore, we propose a systematic analysis that enables an in-depth evaluation of attacks, their interconnections, and cascading effects across different layers. This research intends to contribute to the development of robust security strategies that can mitigate vulnerabilities and increase confidence in decentralized systems by providing a structured technique for analyzing blockchain security concerns. Ultimately, this research underscores the critical need for continuous advancements in blockchain security mechanisms to ensure the resilience of blockchain based systems against emerging and evolving threats.

We present an analytical model relating FPGA architectural parameters to the routability of the FPGA. The inputs to the model include the channel width and the connection and the switch block flexibilities. The output is an estimate of the proportion of nets in a large circuit that can be expected to be successfully routed on the FPGA. We assume that the circuit is routed to the FPGA using a single-step combined global/detailed router. We show that the model correctly predicts routability trends. We also present an example application to demonstrate that this model may be a valuable tool for FPGA architects. When combined with the earlier works on analytical modeling, our model can be used to quickly predict the routability without going through any stage of an expensive CAD flow. We envisage that this model will benefit FPGA architecture designers and vendors to quickly evaluate FPGA routing fabrics.

We present an analytical model relating FPGA architectural parameters to the routability of the FPGA. The inputs to the model include the channel width and connection and switch block flexibilities, and the output is an estimate of the proportion of nets in a large circuit that can be expected to be routed on the FPGA. We assume that the circuit is routed to the FPGA using a single-step combined global/detailed router. Together with the earlier works on analytical modeling, our model can be used to predict the routability without going through an expensive CAD flow. We show that the model correctly predicts routability trends.

FPGA architects typically use experimental techniques to design new architectures. These techniques are time consuming, thus limiting the number of the architectures that can be investigated. Some previous works use analytical models to significantly accelerate the design of a new architecture. To properly capitalize on the benefits of the analytical models, the designers need to have an understanding of the capabilities and the limitations of the analytical models. In this paper, we use two representative architecture questions to provide such understanding. These two questions respectively investigate the optimization of a general-purpose FPGA architecture and the optimization of an application-specific FPGA architecture. For an optimized general purpose architecture, we show that the conclusions made by the analytical models are similar to the experimental techniques, with respect to three different design goals: area, delay and area-delay trade-off. This justifies the use of the analytical models in optimizing general-purpose FPGA architectures. We also find that the analytical models can not capture the behavior of `some' applications that contain `discrete effects'. We present this later finding and the related explanations to show that the analytical models can not optimize application-specific architectures in some cases.

This paper presents an analytical model that relates FPGA architectural parameters to the logic size and depth of an FPGA implementation. In particular, the model relates the lookup-table size, the cluster size, and the number of inputs per cluster to the amount of logic that can be packed into each lookup-table and cluster, the number of used inputs per cluster, and the depth of the circuit after technology mapping and clustering. Comparison to experimental results shows that our model has good accuracy. We illustrate how the model can be used in FPGA architectural investigations to complement the experimental approach. The model's accuracy, combined with the simple form of the equations, make them a powerful tool for FPGA architects to better understand and guide the development of future FPGA architectures.

This paper describes an analytical model that relates the architectural parameters of an FPGA to the average prerouting wirelength of an FPGA implementation. Both homogeneous and heterogeneous FPGAs are considered. For homogeneous FPGAs, the model relates the lookup-table size, the cluster size, and the number of inputs per cluster to the expected wirelength. For heterogeneous FPGAs, the number and positioning of the embedded blocks, as well as the number of pins on each embedded block is considered. Two applications of the model to FPGA architectural design are also presented.

This paper presents an analytical model that relates FPGA architectural parameters to the expected speed of FPGA implementation. More precisely, the model relates the lookup-table size, cluster size, and number of inputs per cluster to the depth of the circuit after technology mapping and after clustering. Comparison to experimental results with large MCNC circuits shows that our models are accurate. We show how the models can be used in FPGA architectural investigations to complement the more usual experimental approach.

We propose a general architecture and implementation for the autonomous assessment of the health of arbitrary service elements, as a necessary prerequisite to self-control. We describe a health engine, the central component of our proposed 'self-awareness and control' architecture. The health engine combines domain independent statistical analysis and probabilistic reasoning technology (Bayesian networks) with domain dependent measurement collection and evaluation methods. The resultant probabilistic assessment enables open, non-hierarchical communications about service element health. We demonstrate the validity of our approach using HP's corporate email service and detecting email anomalies: mail loops and a virus attack.