In an attempt to follow biological information representation and organization principles, the field of neuromorphic engineering is usually approached bottom-up, from the biophysical models to large-scale integration in silico. While ideal as experimentation platforms for cognitive computing and neuroscience, bottom-up neuromorphic processors have yet to demonstrate an efficiency advantage compared to specialized neural network accelerators for real-world problems. Top-down approaches aim at answering this difficulty by (i) starting from the applicative problem and (ii) investigating how to make the associated algorithms hardware-efficient and biologically-plausible. In order to leverage the data sparsity of spike-based neuromorphic retinas for adaptive edge computing and vision applications, we follow a top-down approach and propose SPOON, a 28-nm event-driven CNN (eCNN). It embeds online learning with only 16.8-% power and 11.8-% area overheads with the biologically-plausible direct random target projection (DRTP) algorithm. With an energy per classification of 313nJ at 0.6V and a 0.32-mm2area for accuracies of 95.3% (on-chip training) and 97.5% (off-chip training) on MNIST, we demonstrate that SPOON reaches the efficiency of conventional machine learning accelerators while embedding on-chip learning and being compatible with event-based sensors, a point that we further emphasize with N-MNIST benchmarking.

Recent trends in the field of artificial neural networks (ANNs) and convolutional neural networks (CNNs) investigate weight binarization for full on-chip weight storage to minimize circuit resources and to avoid the high energy cost of off-chip memory accesses. In parallel, spiking neural network (SNN) architectures are explored to further reduce power when processing sparse event-based data streams, while on-chip spike-based online learning targets applications constrained in power and resources during the training phase. However, leveraging high-density on-chip online learning in binary-weight SNNs is still an open challenge. In this work, we demonstrate MorphIC, a quad-core binary-weight digital neuromorphic processor embedding a stochastic version of the spike-driven synaptic plasticity (S-SDSP) learning rule and a hierarchical routing fabric for large-scale chip interconnection. The MorphIC SNN processor embeds a total of 2k leaky integrate-and-fire (LIF) neurons and more than two million plastic synapses for an active silicon area of 2.86mm2in 65nm CMOS, achieving a high density of 738k synapses/mm2.

Neuromorphic engineering aims at building cognitive systems made of electronic neuron and synapse circuits. These emerging computing architectures have a high potential for real-world problems that are difficult to formalize and program, such as vision or sensorimotor control. In order to leverage the potential of neuromorphic engineering and study cognition principles in physical systems, the development of autonomous online learning is a key feature. However, to develop scalable systems that can be used in realistic applications, it is crucial to design compact and low-power hardware platforms. Here we analyze a spike-driven synaptic plasticity (SDSP) learning rule and show that it is particularly well suited for highly compact digital synapse implementations, especially if compared to conventional spike-timing-dependent plasticity (STDP) rules. Furthermore, we designed an asynchronous fully-synthesizable digital synapse circuit with embedded SDSP-based online learning features, and with programmability options for versatile computing. The proposed synapse implementation requires only 20 gates for a compact area of 25μm2 in a 28nm FDSOI CMOS process.

Single-Event Effects are an increasingly important issue in electronic circuits due to technology scaling, efficient error detection schemes are thus required for circuits dedicated to radiative environments, such as in space applications. This work shows that the widespread spatial and temporal redundancy schemes exhibit widely different performances depending on technology, environment and circuit architecture parameters. Following these results, three new redundancy schemes are proposed and compared: one of them, the Forward Temporal Redundancy, stands out as it achieves full error detection with limited timing penalty at only 100% sequential and 45% combinational overheads for a benchmark pipelined MIPS microprocessor.

In the context of wireless sensor nodes for the Internet-of-Things, there is a need for low-power high-performance computing cores for video monitoring applications. In this paper we present a custom 50MHz 32-bit microcontroller running at 0.37V built on a 65nm LP/GP CMOS process. Part of an energy-harvesting SoC with on-chip CMOS imager, it features adaptive voltage scaling, low-power 1.55μW sleep mode, and a variable-width SIMD pipeline and multiply/divide unit, achieving 7.7μW/MHz overall.

With the advent of mobile electronics requiring ever more computing power from a limited energy supply, there is a need for efficient systems capable of maximizing this ratio. Architectural enhancements must therefore be designed to enable high performance, all the while maintaining the power advantage. The technique proposed in this paper allows the acceleration of combinatorial circuits beyond the performance generally achievable by conventional synthesis and timing closure, by exploiting the data-dependent delay variations inherent in such circuits. Through the automatic insertion of transition detectors within the target circuit, the progress of operations underway can be monitored and prematurely completed, thereby increasing the operation speed from the worst toward the average case. In addition, a synthesis flow is proposed to increase the proportion of fast paths, thereby increasing the technique's impact. The proposed technique was applied automatically to a series of benchmark circuits, and the synthesis results show it to achieve good performance, with an average increase of 29% over conventional synthesis, for an average energy increase of${<}{21\%}$overall.

This article proposes a circuit-switched router that combines Spatial Division Multiplexing (SDM) and Time Division Multiplexing (TDM) in order to increase path diversity in the router while sharing channels among multiple connections. In this way, the probability of establishing paths through the network is increased, thereby significantly reducing contention in the network. Furthermore, Quality of Service (QoS) is easily guaranteed. The proposed router was synthesized on an Stratix III 3SL340F FPGA device. A 4 × 4 2D Mesh SDM-TDM Network-on-Chip (NoC) was built with the proposed router and synthesized on the 3SL340F FPGA device. The 4 × 4 2D Mesh SDM-TDM NoC was used to build on an FPGA device, a Multiprocessor System-on-Chip (MPSoC) platform consisted of 16 Nios II/f processors, 16 20-KB On-chip Memories, and 16 Network Interfaces. Synthesis results of the MPSoC platform show that the proposed router architecture can be used to built large practicable MPSoC platforms with the proposed NoC architecture with a reasonable hardware overhead and appreciable clock frequency. Simulation results show that combining SDM and TDM techniques in a router allows the highest probability of establishing paths through the network.

In this paper we propose a hybrid network-on-chip "NoC", which combines SDM-based circuit switching and packet switching in order to efficiently and separately handle streaming and best-effort traffics generated by real-time applications. The proposed NoC thus consists of two sub-networks. The SDM technique is used in circuit-switched sub-network in order to increase path diversity, thereby improving throughput and mitigating low resource utilization, while the packet-switched sub-network is kept as simple as possible. In this way QoS is easily guaranteed without having to share resources which often leads to a complex design. The SDM approach takes advantage of the wire abundance resulting from the increasing density of CMOS circuits. Synthesis results on a FPGA and ASIC show that a practical hybrid network-on-chip can then be built using the proposed approach.

In ultra-low-power applications with long standby periods, power-gating technique can be combined with sub-threshold operation to minimize energy. However, in nanometer technologies, we show in this paper that the introduction of the sleep transistor threatens subthreshold circuit robustness because of noise margin degradation. An increase in Vddto maintain robustness limits the achievable sleep-mode leakage power reduction to 100× with up to 60% active-mode energy penalty. We therefore propose a framework to engineer the sleep transistor under robustness constraint, which shows that a std-Vtlong-channel MOSFET is the optimum sleep transistor with 170× leakage reduction at only 20% energy penalty.

Real-Time applications generate both streaming and best-effort traffics. The on-chip interconnection network for these applications must be able to guarantee Quality of Service "QoS" for streaming traffic and no packet loss for best-effort traffic. In order to efficiently handle both streaming and best-effort traffic, we propose in this paper a hybrid network on chip architecture, which combines CDMA-based circuit switching, packet switching and CDMA-based bus. We show that with the proposed architecture, bounds on latency and throughput can be configurable according to application constraints, thereby meeting QoS requirements in a hybrid traffic environment.

Subthreshold operation of digital circuits enables minimum energy consumption. In this article, we observe that minimum energy E min of subthreshold logic dramatically increases when reaching 45nm CMOS node. We demonstrate by circuit simulation and analytical modeling that this increase comes from the combined effects of variability, gate leakage, and Drain-Induced Barrier Lowering (DIBL) effect. We then investigate the new impact of individual MOSFET parameters L g , V t , and T ox on E min in sub-45nm technologies. We further propose an optimum MOSFET selection, which favors low-V t mid-L g devices in 45nm CMOS technology. The use of such optimum MOSFETs yields 35% E min reduction for a benchmark multiplier with good speed performances and negligible area overhead. This optimum MOSFET selection can easily be integrated into a standard EDA tool flow by appropriate selection of the standard cell library. We finally demonstrate that undoped-channel fully-depleted Silicon-On-Insulator (SOI) technology brings 60% E min reduction with baseline MOSFETs thanks to strong mitigation of variability and short-channel effects. This study reveals a new (à priori counterintuitive) paradigm in device optimization for subthreshold logic: relaxing gate leakage constraints to improve robustness against short-channel effects and variability. Additionally, we propose pre-Silicon BSIM4 MOSFET model cards for realistic subthreshold circuit simulations including variability in bulk and fully depleted SOI technologies, which are made available online.

We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show that technology flavor and Vt selections shift minimum-energy point to different operating frequencies, thereby enabling minimum energy in either low- or mid-performance applications. However, we demonstrate that independent dual-Vt assignment to save leakage in non-critical paths is not feasible. We then show that reverse adaptive body biasing (ABB) is potentially more efficient to compensate for global process/temperature variations than adaptive voltage scaling and forward ABB. Nevertheless, its practical efficiency is limited by the affordable VBB range and the value of the body-effect coefficient.

In this paper, we observe that minimum energy Emin of subthreshold logic dramatically increases when reaching 45nm node. We demonstrate by circuit simulation and analytical modeling that this increase comes from the combined effects of variability, gate leakage and DIBL. We then investigate the new impact of MOSFET parameters on Emin in nanometer technologies. We finally propose an optimum MOSFET selection intended for subthreshold circuit designers, which favors low-Vt mid-Lg devices in standard 45nm GP technology. The use of such optimum MOSFETs yields 35% Emin reduction for a benchmark multiplier with good speed performances and negligible area overhead.

Today, available embedded automotive systems offer valuable services and allow building highly added value applications in transports and logistics. However the fast changing needs in this market have added more constraints on the design process of theses systems. Making such systems easy to upgrade according to the latest technologies, new data sources and requirements while coping with time to market and cost constraints is a real challenge. Efficient and flexible hardware/software platform design is a good approach to deal with this goal. This paper presents an automotive system designed to allow objective coaching and monitoring of the driving behavior of truck drivers. The system collects and processes data from a variety of in-vehicle sensors and interfaces. It describes our embedded platform and shows how it was efficiently adapted for a custom automotive application by allowing easy hardware integration and software support for specific new sensors and interfaces according to the evolving needs of the final customer.

Subthreshold logic is an efficient technique to achieve ultralow energy per operation for low-to-medium throughput applications. In this paper, the interests and limitations of technology scaling for subthreshold logic are investigated from 0.25 mum to 32 nm nodes. Scaling to 90/65 nm nodes is shown to be highly desirable for medium-throughput applications (1-10 MHz) due to great dynamic energy reduction. However, this interest is limited at 45/32 nm nodes by high static energy due to degraded subthreshold swing and delay variability. Moreover, for low-throughput applications (10-100 kHz), this limitation is worsened by the increase of minimum supply voltage to achieve sufficient functional yield, which results in bad energy efficiency starting at 0.13 mum node. Upsizing the channel length is proposed as a straightforward circuit-level technique to efficiently mitigate these effects. At 32 nm node, this technique reduces energy per operation by 60% at medium throughput and by two orders of magnitude at low throughput.

Over the last decade, the design of ultra-low-power digital circuits in subthreshold regime has been driven by the quest for minimum energy per operation. In this contribution, we observe that operating at minimum-energy point is not straightforward as design constraints from real-life applications have an important impact on energy. Therefore, we introduce the alternative concept of practical energy, taking functional-yield and throughput constraints on minimum Vddinto account. In this context, we demonstrate for the first time the detrimental impact of DIBL on minimum Vdd. Practical energy gives a useful analysis framework of circuit optimization to reach minimum-energy point, while considering the throughput as an input variable dictated by the application. From simulation of a benchmark multiplier in 45 nm technology, we find out that practical energy can be far higher than minimum energy point, in the case of low-throughput applications (ap 10-100 kOp/s) because of static leakage energy and robustness-limited minimum Vdd. With the proposed framework, we investigate the capability of conventional optimization techniques to make practical energy meet minimum energy point. Amongst these techniques, channel length upsize is shown to be more efficient than MTCMOS power gating, body biasing, Vt selection or device width upsize, as it increases robustness while simultaneously reducing static leakage energy. A small length upsize with low area overhead is shown to reduce practical energy at low throughput to less than 2.1 times the minimum energy level. At medium throughput, it even brings practical energy 30% lower than minimum energy level without optimization techniques.

This paper presents the RECOPS project that aims to study the use of reconfiguration in military applications. The project explores the new potentials and possibilities offered by reconfigurable components like FPGA. It identifies specificities related to the use of this technology in military applications and proposes solutions to support them. Specific techniques like dynamic reconfiguration or high speed serial I/Os are also covered. The paper gives a description of the project and then presents preliminary results on the advantages and impacts of using reconfiguration in military applications. It also gives a synthetic view of the needs and challenges that need to face this technology to be integrated in professional and military electronics applications. They are based on a study made over a broad range of seven demonstrators covering most of the fields of military applications

As the trend in reconfigurable electronics goes towards strong integration, FPGA devices are becoming more and more interesting. They are already used for safety-critical applications such as avionics (Hispano-Suiza, 2005). Latest FPGA's also enable new techniques such as dynamic partial reconfiguration (DPR), allowing new possibilities in terms of performance and flexibility. Their use in safety-critical systems is considered as impossible nowadays since they must be strictly validated, and DPR brings many new issues. Indeed, the tools used for DPR must be certified, which is barely impossible for the current DPR tools provided by the vendors. We have developed a simple flow upon the usual static one for Xilinx FPGA's that does not require any support of the vendor tools for DPR. This lessens the complexity of tools certification, and make a step towards enabling the certification of DPR for safety-critical applications. Moreover, under strong hypotheses, and by using safe design principles, we show how the complexity of certifying DPR can be reduced

With the increasing capacity of FPGAs following the Moore's law, it is possible to build in a single FPGA, a large system on chip (SoC) composed by several cores. Their performances depend strongly on their interconnection structure. Traditional and hierarchical busses are not suitable to be used. The Networks on Chip (NoC), due to their characteristics such as scalability, flexibility, high bandwidth, have been proposed as a valid approach to meet communication requirements in SoC. Most of the current NoCs uses mesh topology. With mesh topology, central channels are significantly solicited. This often leads to the congestion of the center area of the mesh. The solution for such situation is to add routers in the mesh or to use torus topology which, with the symmetry introduced on the routers in the opposite edges, has a good behavior to face congestion, and this, with a small increase of resources. In this paper, we propose a scalable implementation of a NoC for FPGA using torus topology. We proposed router architecture, a routing algorithm and a solution to the problem introduced by the long wires in torus topology.

This paper proposes different low-cost coprocessors for public key authentication on 8-bit smart cards. Elliptic curve cryptography is used for its efficiency per bit of key and the Elliptic Curve Digital Signature Algorithm is chosen. For this functionality, an area constrained coprocessor is probably the best approach to perform the most computer-intensive operations at an acceptable speed considering the limited memory and power of the selected platform. For that purpose, the scalar point multiplication in GF(2m) in both affine and projective coordinates was implemented in order to compare their performances with the same level of optimization and the same technology. A hardware/ software co-design strategy was also used to avoid the need of a dedicated register file.

Embedded systems allow application-specific optimizations to improve the power/performance trade-off. In this paper, we show how application-specific hashing of the address can eliminate a large number of conflict misses in caches. We consider XOR-functions: each set index bit is computed as the XOR of a subset of the address bits. Previous work has considered simpler bit-selecting functions. Compared to such work, the contributions of this paper are two-fold. Firstly, we present a heuristic algorithm to construct application-specific XOR-functions. Secondly, in order to adapt the hashing to the application, we show that a reconfigurable XOR-function selector is inherently less complex than a reconfigurable selector for bit-selecting functions. This is possible by placing restrictions on the allowed XOR-functions. Our evaluation shows a reduction of cache misses for standard benchmarks averaging between 30% and 60%, depending on the cache size

<?Pub _touchup WordspNominal="1.6" WordspMinimum="1.3" WordspMaximum="2.9"?>The image compression standard JPEG 2000 proposes a large set of features that is useful for today's multimedia applications. Unfortunately, it is much more complex than older standards. Real-time applications, such as digital cinema, require a specific, secure, and scalable hardware implementation. In this paper, a decoding scheme is proposed with two main characteristics. First, the complete scheme takes place in a field-programmable gate array without accessing any external memory, allowing integration in a <?Pub /_touchup?>secured system. Second, a customizable level of parallelization allows to satisfy a broad range of constraints, depending on the signal resolution. The resulting architecture is therefore ready to meet upcoming digital cinema specifications.

This paper presents a hardware implementation of a decoder for Digital Cinema images. This decoder enables us to deal with image size of 2K with 24 frames per second and 36 bits per pixels. It is the first implementation known nowadays that perfectly fits in one single Virtex-II® FPGA and includes AES decryption, JPEG 2000 decompression and fingerprinting blocks. This hardware offers therefore high-quality image processing as well as robust security.

We propose a new mathematical DES description that allows optimized implementations. It also provides the best DES and triple-DES FPGA implementations known in term of ratio throughput/area, where area means the number of FPGA slices used. First, we get a less resource consuming unrolled DES implementation that works at data rates of 21.3 Gbps (333 MHz), using VIRTEX II technology. In this design, the plaintext, the key and the mode (encryption/decrytion) can be changed on a cycle-by-cycle basis with no dead cycles. In addition, we also propose sequential DES and triple-DES designs that are currently the most efficient ones in term of resources used as well as in term of throughput. Based on our DES and triple-DES results, we also set up conclusions for optimized FPGA design choices and possible improvement of cipher implementations with a modified structure description.

Reprogrammable devices such as Field Programmable Gate Arrays (FPGA's) are highly attractive options for hardware implementations of encryption algorithms and this report investigates a methodology to efficiently implement block ciphers in CLB-based FPGA's. Our methodology is applied to the new Advanced Encryption Standard RIJNDAEL and the resulting designs offer better performances than previously published in literature. We propose designs that unroll the 10 AES rounds and pipeline them in order to optimize the frequency and throughput results. In addition, we implemented solutions that allow to change the plaintext and the key on a cycle-by-cycle basis with no dead cycles. Another strong focus is placed on low area circuits and we propose sequential designs with very low area requirements. Finally we demonstrate that RAM-based implementations implies different constraints but our methodology still holds.

In its basic version, linear cryptanalysis is a known-plaintext attack that uses a linear relation between input-bits, output-bits, and key-bits of an encryption algorithm that holds with a certain probability. If enough plaintext-ciphertext pairs are provided, this approximation can be used to assign probabilities to the possible keys and to locate the most probable one. Matsui (1993) applied it to DES, becoming the best known attack against DES. Knudsen (2000) proposed three chosen-plaintext linear attacks, the third one becoming the best chosen-plaintext attack. This paper presents two original FPGA implementations of a DES encryption/decryption core that work at data rates up to 21.3 Gbps (333 MHz). We believe that our implementations are the fastest ones known nowadays. In our design, the plaintext, the key, and the mode (encryption/decryption) can be changed with no dead cycles. Based on one of our fast DES implementations, we present an FPGA implementation of the known-plaintext linear cryptanalysis of DES. The resulting design is deployed on eight FPGAs and allows us to find 12+1 key bits in about 2.3 hours. As a comparison, the fastest software implementation known so far (in 2000) used the idle time of 18 Intel Pentium III MMX and broke a DES key in 4.32 days. Our fast linear cryptanalysis implementation made the performing of practical tests possible, allowing a comparison with Matsui's theoretical estimations.

The wavelet transform is a very promising tool for image compression. In JPEG2000, two filter banks are used, one an integer lossless 5-3 filter, and one a lossy 9-7. A combined architecture for the 5-3 and 9-7 transforms with minimum area is presented. The lifting scheme is used to realize a fast wavelet transform. Two lines are processed at a time. This line-based architecture allows minimum memory requirement and fast calculation. The pipeline and the optimization of the operations provide speed, while the combination of the two transforms in one structure contributes to saving the area. On a VIRTEXE1000-8 FPGA implementation, decoding of 2 pixels per clock cycle can be performed at 110 MHz. Only 19% of the total area of the VIRTEXE1000 is needed. Compared to existing architectures, memory resource and area can be reduced thanks to the proposed solution.

In the context of parallel processing and reconfigurable computing, new high-density reconfigurable devices offer unexplored possibilities in various areas. Floating point operations, previously reserved to dedicated hardware, can now be mapped on reconfigurable machines. In this area, robotic algorithms require the computation of large dataflow graphs. Present DSP do not provide an efficient way of implementing parallel processing in such applications. This paper presents an original application of a data driven architecture applied to robotic. Target architecture is a multi-FPGA platform equivalent to 400.000 gates. Results show that current reconfigurable devices could deliver powerful computations (true 720 MFLOPs) compared to DSP.

This paper presents a compression scheme for digital still images, by using the Kohonen's neural network algorithm, not only for its vector quantization feature, but also for its topological property. This property allows an increase of about 80% for the compression rate. Compared to the JPEG standard, this compression scheme shows better performances (in terms of PSNR) for compression rates higher than 30.

We introduce an algorithm for visual prosthesis devices, where the data bandwidth must be dramatically reduced in order to correspond to the biotechnological constraints. The resolution reduction is based on an image segmentation by growth of zones which gives good results and allows an implementation in a low-power VLSI device.

In this paper, we present systolic architecture based on the lattice structure of filters. The main characteristic of this architecture is the systolism: computations are pipelined in many identical locally interconnected processing elements (PEs). These PEs are simple and can reach high frequency clock while working at any time of the process. So, the speed of the circuit can be increased. The implementation of the filters, through VLSI techniques, is facilitated by the repetitive nature of the elements. In section 2, we describe the multiresolution scheme and the lattice structures. If the lattice structure appears as an efficient remedy for the finite length of the multipliers, special attention has to be kept on the computation noise which appears when the datapath is limited to some finite width. The goal of the so-related study consists in keeping this computation noise below the quantization noise (coming from the quantizers) at a reasonable cost. In section 3, we present the basic processing element and its use among the different stages of the filter. Section 4 deals with the finite representation of the data throughout the datapath.

Kohonen maps are self-organizing neural networks that classify and quantify n-dimensional data into a one- or two-dimensional array of neurons. Most applications of Kohonen maps use simulations on conventional computers, eventually coupled to hardware accelerators or dedicated neural computers. The small number of different operations involved in the combined learning and classification process, however, makes the Kohonen model particularly suited to a dedicated VLSI implementation, taking full advantage of the parallelism and speed that can be obtained on the chip. A fully analog implementation of a one-dimensional Kohonen map, with on-chip learning and refreshment of on-chip analog synaptic weights, is proposed. The small number of transistors in each cell allows a high degree of parallelism in the operations, which greatly improves the computation speed compared to other implementations. The storage of analog synaptic weights, based on the principle of current copiers, is emphasized. It is shown that this technique can be used successfully for the realization of VLSI Kohonen maps.

This paper describes a new parallel architecture dedicated to multi-motion estimation. The input image is scanned by a standard video camera with 256 grey levels. Motion computing is based on the optical flow determination. Some constraints are proposed to allow multi-motion evaluation. The algorithm is presented and the main features of a 1-D systolic architecture which is based on a custom VLSI chip is given. This architecture allows a real-time implementation of the multi-motion estimation algorithm.>