Object clustering is a data structure expressly binding analysis to support the incremental symbolic synthesis of high performance VLSI devices. Utilization of abstraction allows technology independent and technology dependent design entities to be represented as symbolic objects. This data structure supports a hierarchical representation of a VLSI device that equally applies to top-down or bottom-up synthesis. Processing concurrency is exploited in an interactive design environment centered around commercially available CAD work stations. As the designer is interactively composing the symbolic representation of circuit topology to implement a specific function, a rules-based algorithm performs the integration of the new object into the existing object clustering data structure. Neighboring relationships between objects are determined by hierarchical object-pair intersection and underlie the algorithms performing electrical and physical design rule checking, node topology extraction for circuit analysis, logic simulation, and testability analysis, and mask geometries generation. Object clustering is a robust data structure ideally suited to symbolically represent VLSI device designs, while facilitating analytical exploration and incremental synthesis.

In the computer-aided design of digital equipment, by the time a wire unit is in the check-out lab, a large amount of information concerning this unit exists in the form of tape files. Since our D.A. System is entered via logic equations, we have a file containing this information, plus files indicating the partitioning of the equations, the placement of smaller building blocks within larger building blocks, and the assignment of signals to pins for routing or wiring. Also, there will be a wire list file (or a router output file) plus a punch card deck when a wiring machine is to be used. In addition a large pile of computer output reports will exist communicating this information to the literate world. About two years ago we learned that in some of the checkout labs engineers were devoting large amounts of time pouring through the reports we generate in order to correlate signals appearing in logic equations with connector pins. In order to remove this burden from these engineers, a program known as the Equation Connector Program (EQNCON) was written. This program exhibits the correlation of logic signals and connector pins in a printed report which is then heavily used during checkout.

One of the most perplexing problems confronting device designers utilizing MOS technology is the development of an effective layout design methodology. This paper describes a versatile layout design scheme for customized digital-type MOS arrays utilizing four-phase clocking schemes (ratioless logic). The analytical characterization of this layout design scheme is defined through the introduction of p-order and m-order indices. The p-order indices are assigned to members of the Boolean equation set that define the relative placement of their mechanization areas (p-diffusion structures) on the MOS array. The m-order indices are assigned to members of the term set that define their relative placements within parallel metalization channels on the MOS array. The underlying variables influencing the algorithmic derivation of quasi-optimal p-order and m-order assignments are also discussed.