Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from VLDB 2026 / reviewers in the wild / expert

R. L. Maiasz

dblp:17/3375 · DBLP profile ↗
← Back
1ranked-venue papers
1as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 91% Integrated circuit design · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design
cell layout		 0.011987
Layout Optimization of CMOS Functional Cells · DAC 1987
Electronic design automation › physical design › cell layout
CMOS cell layout		 0.011987
Layout Optimization of CMOS Functional Cells · DAC 1987
Electronic design automation
physical design		 0.011987
Layout Optimization of CMOS Functional Cells · DAC 1987
Integrated circuit design › ASIC design
standard cell design		 0.011987
Layout Optimization of CMOS Functional Cells · DAC 1987

Methods — techniques the papers use, named apart from their topics

graph-theoretical framework · 0.0
YearPublicationVenuePosition
1987 Layout Optimization of CMOS Functional Cells
abstract
An optimal non-exhaustive method of minimizing the layout area of complementary series-parallel CMOS functional cells in the standard-cell style is presented. This generalizes earlier work of Uehara and van Cleemput which is heuristic and nonoptimal. A complete graph-theoretical framework for CMOS cell layout is developed and illustrated. The approach demonstrates a new class of graph-based algebras which characterize this layout problem.
R. L. Maiasz, John P. Hayes
 DAC1