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Leif Olsson

dblp:17/3641 · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Security and privacy · 1Graphics, computer vision, multimedia, augmented reality and games · 1Human-computer interaction and ubiquitous computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Embedded and real-time systems · 33% Memory systems · 33% Electronic design automation · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
high-level synthesis
0.112007
Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007
Memory systems › memory hierarchy
memory hierarchy optimization
0.112007
Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007
Embedded and real-time systems › real-time signal processing
real-time video processing
0.112007
Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007

Methods — techniques the papers use, named apart from their topics

integer nonlinear programming · 0.1
YearPublicationVenuePosition
2019 Mitigating Escalation of Cascading Effects of a Payment Disruption Across Other Critical Infrastructures: Lessons Learned in 15 Simulation-Games
Joeri van Laere, Björn J. E. Johansson, Leif Olsson, Peter Määttä
CRITIS3
2017 Analyzing the Implications of Design Choices in Existing Simulation-Games for Critical Infrastructure Resilience
Joeri van Laere, Osama Ibrahim, Aron Larsson, Leif Olsson, Björn J. E. Johansson, Per M. Gustavsson
ISAGA4
2007 Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems
abstract
The great variety of pixel dynamics of real-time video-processing systems (RTVPS), ranging from color, grayscale, or binary pixels, means that a careful design and specification of bit widths is required. It is obvious that the bit-width specification will affect the total memory storage requirement. However, what is not so obvious is that the bit-width specification will also affect the design of the memory hierarchy, an impact similar for both hardware and software implementations. We have developed an integer-nonlinear-program formulation for the optimization of the memory hierarchy of RTVPS. An active surveillance video camera is introduced as a test case. We demonstrate how the optimization model can reduce the on-chip memory storage by 61% compared to a nonoptimal memory hierarchy.
Benny Thörnberg, Martin Palkovic, Qubo Hu, Leif Olsson, Per Gunnar Kjeldsberg, Mattias O'Nils, Francky Catthoor
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4