Ultrasonic Local Positioning Systems (U-LPS) can be used for fine-grained indoor positioning. Typically, multiple fixed beacons simultaneously emit ultrasonic signals whose time of arrival is estimated at a mobile receiver. The ultrasonic signals are encoded and modulated to allow separation of the signals at the receiver, identification of the transmitters, and mitigation of signal impairments such as multipath, the near-far effect, multiple access interference, and Doppler shift. Hence, waveform design (coding and modulation) plays a pivotal role in determining the performance of such a system. This paper compares the performance of four modulation techniques (specifically QPSK, OFDM, Slow-FHSS and Fast-FUSS) transmitting Zadoff-Chu (ZC) sequences in an U-LPS. The modulation schemes are evaluated in terms of time of arrival accuracy and positioning accuracy in simulation and real-world experiments. Simulation and, to a lesser extent, real-world tests indicate that ZC coded QPSK modulation with non-coherent detection using a matched filter, offers greater accuracy under realistic conditions than the other modulation schemes.

Wireless Sensor Network (WSN) technology has recently moved out of controlled laboratory settings to real-world deployments. Many of these deployments experience high rates of failure. Common types of failure include node failure, link failure, and node reboot. Due to the resource constraints of sensor nodes, existing techniques for fault detection in enterprise networks are not applicable. Previously proposed WSN fault detection algorithms either rely on periodic transmission of node status data or inferring node status based on passive information collection. The former approach significantly reduces network lifetime, while the latter achieves poor accuracy in dynamic or large networks. Herein, we propose Sequence-Based Fault Detection (SBFD), a novel framework for network fault detection in WSNs. The framework exploits in-network packet tagging using the Fletcher checksum and server-side network path analysis to efficiently deduce the path of all packets sent to the sink. The sink monitors the extracted packet paths to detect persistent path changes which are indicative of network failures. When a failure is suspected, the sink uses control messages to check the status of the affected nodes. SBFD was implemented in TinyOS on TelosB motes and its performance was assessed in a testbed network and in TOSSIM simulation. The method was found to achieve a fault detection accuracy of 90.7% to 95.0% for networks of 25 to 400 nodes at the cost of 0.164% to 0.239% additional control packets and a 0.5% reduction in node lifetime due to in-network packet tagging. Finally, a comparative study was conducted with existing solutions.

This paper proposes a novel approach to the problem of indoor location estimation based on IEEE 802.11 (WiFi) signals. The approach uses a rotating directional antenna at the Access Point (AP). The Mobile Device (MD) measures the variation of Received Signal Strength Indication (RSSI) with antenna Direction Of Emission (DOE). The observed DOE-RSSI signature is used as a fingerprint to search a map of previously measured DOE-RSSI signatures. The method has the advantage that it works with existing 802.11 cards and that it provides higher accuracy, for the same number of APs, than the conventional RSSI fingerprinting technique based on maps obtained using multiple omnidirectional APs. We report results obtained from an experimental testbed deployed in a typical office space. The Lighthouse algorithm achieved 85% and 95% success ratio in MD localisation over 20 possible positions using one AP and two APs, respectively. The success ratio achieved is, on average, +24% and +53% better than the conventional RSSI fingerprinting and directional beaconing methods, respectively.

This paper studies the problem of designing a low complexity Concurrent Error Detection (CED) circuit for the complex multiplication function commonly used in Digital Signal Processing circuits. Five novel CED architectures are proposed and their computational complexity, area, and delay evaluated in several circuit implementations. The most efficient architecture proposed reduces the number of gates required by up to 30 percent when compared with a conventional CED architecture based on Dual Modular Redundancy. Compared to a Residue Code CED scheme, the area of the proposed architectures is larger. However, for some of the proposed CEDs delay is significantly lower with reductions exceeding 30 percent in some configurations.

Wireless sensor networks (WSN) show enormous potential for collection and analysis of physical data in real-time. Many papers have proposed methods for improving the network reliability of WSNs. However, real WSN deployments show that sensor data-faults are very common. Several server-side data reliability techniques have been proposed to detect these faults and impute missing or erroneous data. Typically, these techniques reduce the lifetime of the network due to redundant data transmission, increase latency, and are computation and storage intensive. Herein, we propose Packet-Level Attestation (PLA), a novel framework for sensor data reliability assessment. It exploits the spatial correlation of data sensed at nearby sensors. The method does not incur additional transmission of control message between source and sink; instead, a verifier node sends a validation certificate as part of the regular data packet. PLA was implemented in TinyOS on TelosB motes and its performances was assessed. Simulations were performed to determine its scalability. It incurs only an overhead of 1.45% in terms of packets transmitted. Fault detection precision of the framework varied from 100% to 99.48%. Comparisons with existing methods for data reliability analysis showed a significant reduction in data transmission, prolonging the network lifetime.

Wireless sensor networks (WSNs) are highly resource constrained in terms of power supply, memory capacity, communication bandwidth, and processor performance. Compression of sampling, sensor data, and communications can significantly improve the efficiency of utilization of three of these resources, namely, power supply, memory and bandwidth. Recently, there have been a large number of proposals describing compression algorithms for WSNs. These proposals are diverse and involve different compression approaches. It is high time that these individual efforts are put into perspective and a more holistic view taken. In this article, we take a step in that direction by presenting a survey of the literature in the area of compression and compression frameworks in WSNs. A comparative study of the various approaches is also provided. In addition, open research issues, challenges and future research directions are highlighted.

The promise of 24/7 patient monitoring and online diagnosis using wearable and implantable biomedical devices has engendered significant research interest in the development of low power biosignal processing platforms. A novel Coarse Grained Reconfigurable Array (CGRA) architecture is presented for low power, real time processing of biomedical signals. The proposed architecture differs from previously proposed CGRAs in that it is designed for low power, rather than for high performance. The proposed architecture was implemented in a software modeler and simulator and in Verilog. The architecture was shown to provide average savings in energy consumption of 62% compared to conventional DSP and SIMD processors and average speed ups of 30× and 8×, respectively, for typical biosignal processing algorithms.

A novel concurrent soft error detection and correction scheme is introduced for parallel hardware implementations of transform-based convolution. The proposed technique is based on the structure of radix-2 Fast Fourier Transforms (FFT) of length 2nwhere n is an integer. The scheme can provide up to 100 percent detection and correction of isolated single soft errors in the convolution at the cost of little more than double the system area, rather than triple, as is required when using conventional Triple Modular Redundancy (TMR).

In this article we describe a low-power processor platform for use in Wireless Sensor Network (WSN) nodes (motes). WSN motes are small, battery-powered devices comprised of a processor, sensors, and a radio frequency transceiver. It is expected that WSNs consisting of large numbers of motes will offer long-term, distributed monitoring, and control of real-world equipment and phenomena. A key requirement for these applications is long battery life. We investigate a processor platform architecture based on an application-specific programmable processor core, System-On-Chip bus, and a hardware accelerator. The architecture improves on the energy consumption of a conventional microprocessor design by tuning the architecture for a suite of TinyOS-based WSN applications. The tuning method used minimizes changes to the instruction set architecture facilitating rapid software migration to the new platform. The processor platform was implemented and validated in an FPGA-based WSN mote. The benefits of the approach in terms of energy consumption are estimated to be a reduction of 48% for ASIC implementation relative to a conventional programmable processor for a typical TinyOS application suite without use of voltage scaling.

This article presents an analysis of the reliability of memories protected with Built-in Current Sensors (BICS) and a per-word parity bit when exposed to Single Event Upsets (SEUs). Reliability is characterized by Mean Time to Failure (MTTF) for which two analytic models are proposed. A simple model, similar to the one traditionally used for memories protected with scrubbing, is proposed for the low error rate case. A more complex Markov model is proposed for the high error rate case. The accuracy of the models is checked using a wide set of simulations. The results presented in this article allow fast estimation of MTTF enabling design of optimal memory configurations to meet specified MTTF goals at minimum cost. Additionally the power consumption of memories protected with BICS is compared to that of memories using scrubbing in terms of the number of read cycles needed in both configurations.

This article presents a novel real-time algorithm for reducing and dynamically controlling the computational complexity of an H.264 video encoder implemented in software. A fast mode decision algorithm, based on a Pareto-optimal macroblock classification scheme, is combined with a dynamic complexity control algorithm that adjusts the MB class decisions such that a constant frame rate is achieved. The average coding efficiency of the proposed algorithm was found to be similar to that of conventional encoding operating at half the frame rate. The proposed algorithm was found to provide lower average bitrate and distortion than static complexity scaling.

The structure of radix-2 Fast Fourier Transforms of length 2nwhere n is an integer is used to propose a new soft error detection and correction scheme for transform based convolution. The scheme can provide up to 100% detection and correction of isolated soft errors for, in many cases, approximately double the original system cost in terms of area and/or computational complexity. This is a substantial reduction when compared with conventional Triple Modular Redundancy. The method can be used for both hardware and software implementations of transform-based convolution.

In this letter, we propose a novel method to disambiguate the phase-difference of a single-frequency signal observed between a pair of spatially separated sensors, with inter-sensor spacing exceeding half the wavelength (lambda/2) of the signal. We mathematically prove that, in a noiseless case, the true phase-difference can unambiguously be estimated utilizing a third collinear sensor, provided that the absolute difference between the two smaller inter-sensor spacings is less than lambda/2. The performance of the method is characterized by estimating the probability of failure in noisy cases.

The purpose of this paper is to present a new System-on-Chip bus designed for the application specific requirements of Wireless Sensor Network (WSN) platforms. The bus is designed to support Globally Asynchronous Locally Synchronous (GALS) systems. The bus is multi-rate with delay tolerance to support Dynamic Voltage and Frequency Scaled (DVFS) sub-systems. Unlike traditional buses, the sub-systems operate as peers, rather than as master-slaves. Lowpower features include clock gating when inactive and burst transfers. The bus supports up to 255 interconnected resources.

The H.264 video encoding standard can achieve high coding efficiency at the expense of high computational complexity. Typically, real-time software implementation requires omission of most optional encoding tools leading to significantly reduced coding efficiency. This paper proposes a novel method for real-time H.264 encoding based on dynamic control of the encoding parameters to meet real-time constraints while minimizing coding efficiency loss. Experimental results show that the method provides up to 19% lower bit rate than conventional real-time encoding using fixed parameters with the same visual quality. The method allows real-time 30fps QCIF encoding on a Pentium IV with similar coding efficiency to full search baseline profile encoding.

Estimation of processor current consumption is important for the design of low power systems. This paper proposes a novel method for estimating the dynamic current consumption of a processor. The method models dynamic current as the output of a linear system excited by a signal comprised of the total current due to each instruction. System identification is performed by cross-correlation of a pseudo-random stimulus with the measured current. The method was applied to the Texas Instruments TMS320VC5510 DSP and was found to provide an average correlation of 93% between estimated and measured dynamic current across a range of benchmarks.