With the increasing risk of IP reuse in System on Chip (SoC) design, intellectual property (IP) techniques becomes one of the most important issues. Compare with watermarking, fingerprinting is a more effective method because is not only protects the IP owner's benefits but also user's rights. In this paper, we firstly propose a multilevel fingerprinting method for IP protection. In the typical field programmable gate array (FPGA) design flow, we first embed the watermarks into a FPGA design at netlist level by manipulating LUTs. When the IP core is compiled into a bitstream file, an individual fingerprint from IP user is then embedded into margin of FPGA. The experimental results show that the method has low resource and timing overhead, while proves a strong certificate both of IP owner and users.

In this paper, we introduce a new watermarking system for IP protection on post-layout design phase. Firstly the copyright is encrypted by DES (Data Encryption Standard) and then embedded by using an incremental router into the layout design. This watermarking technique uniquely identifies the circuit origin, yet is difficult to be detected or fabricated. The incremental router consists of a rip-up and a special re-router that inserts redundant bends into wires probabilistic. We evaluated the technique on various generated benchmark circuits to validate the completeness of the procedure. The results show it achieves almost 100% success for embedding with no extra area cost on design performances.

In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such that a clockinput timing of each register is a multiple of a predefined unit delay and the length of interconnection from a parent node to its child is upper bounded. The clock trees are constructed for several practical circuits. The size of each clock tree is comparable to a zero skew clock tree. In order to assure the practical quality, they are examined under the five delay conditions, which cover various environmental and manufacturing conditions. As a result, they are proved stable under each condition and improve the clock speed up to 17.3 % against the zero skew clock trees. Keywords Semi-synchronous, clock-input timing, clock scheduling, environmental and manufacturing conditions, zero skew clock tree, various timing clock tree. 1.

This paper describes a new clustering approach for VLSI placement, which is based on a fractal dimension analysis for the topological structure of modules in a logic diagram. A distinctive feature of this approach is that the concept of a fractal dimension has been introduced into a logic diagram in such a way that clustering of modules is iterated while the fractal dimension of clustered modules remains in a prescribed range. A part of experimental results is also shown, which demonstrates that our clustering approach achieves better solutions than the conventional placement without clustering.>