Demo Data from VLDB 2026 / reviewers in the wild / expert
Kishore Kota
dblp:17/4275
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1993
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 50% Integrated circuit design · 38% Cloud and datacenter computing · 12% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture
computer arithmetic |
0.0 | 1 | 1993 | Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors · IEEE Trans. Computers 1993 |
Integrated circuit design › digital arithmetic circuits
CORDIC |
0.0 | 1 | 1993 | Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors · IEEE Trans. Computers 1993 |
Cloud and datacenter computing › resource provisioning
dynamic resource provisioning |
0.0 | 1 | 1993 | Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors · IEEE Trans. Computers 1993 |
Processor architecture and microarchitecture
special-purpose processor |
0.0 | 1 | 1993 | Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors · IEEE Trans. Computers 1993 |
Methods — techniques the papers use, named apart from their topics
y-reduction mode · 0.0hybrid architecture · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1993 | Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose ProcessorsabstractThe coordinate rotation digital computer (CORDIC) algorithm is used in numerous special-purpose systems for real-time signal processing applications. An analysis of fixed-point CORDIC in the Y-reduction mode, which allows computation of the inverse tangent function, shows that unnormalized input values can result in large numerical errors. The authors describe two approaches for tackling the numerical accuracy problem. The first approach builds on a fixed-point CORDIC unit and eliminates the problem by including additional hardware for normalization. A method for integrating the normalization operation with the CORDIC iterations for efficient implementation in O(n/sup 1.5/) hardware is provided. The second solution to the accuracy problem is to use a floating-point CORDIC unit but reduce the implementation complexity by using a hybrid architecture. Arguments to support the use of such an architecture in certain special-purpose arrays are presented.> Kishore Kota, Joseph R. Cavallaro |
IEEE Trans. Computers | 1 |