Consideration is given to the implementation of distributed discrete-event simulation (DDES) using what has been commonly called the Misra approach, after one of its inventors. A major problem with DDES is that deadlock can occur. Therefore, DDES algorithms must either avoid deadlock in the first place, or detect the existence of deadlock when it does occur and eliminate it. J. Misra (1986) proposes the use of null messages as one way to circumvent the deadlock problem. However the number of null messages can become quite large. Methods are presented for reducing the number of null messages through the prediction of channel times. A framework is presented on the basis of which distributed discrete-event simulation can be built for applications that can be decomposed into feedforward and feedback networks.>

The relevant definitions are given and a model of self-checking iterative network is presented. A general combinational circuit was developed that is totally self-checking and can detect an error on the input code lines and transmit the error to the output code lines. Thus, an error generated in a cell is transmitted from cell to cell until the last cell is reached. The error, and fault that generated it, can be detected by the checker at the last cell, which can also be made self-checking. The added redundancy increases the amount of logic required to realize the circuit, and the increase depends on the circuit being realized. If z is the number of output code lines for a general cell, a rough estimate of the percent increase in circuitry is 1/z*100.>

The authors present the design of self-checking sequential machines using standard memory elements, i.e. D, T, or JK flip-flops. The design approach involves cascading the three parts of a sequential machine, i.e. excitation, memory elements, and the output circuit. Parity is used to detect and transmit errors from one part to the next. The conditions for testing D, T, and JK flip-flops and for transmitting errors from their inputs to their outputs are presented; these are shown to exist in normal operation when the design procedure is used. SR flip-flops are found not to have the properties necessary for designing self-checking sequential machines.>

Orchard codes are linear, systematic tree codes of rate(n - 1)/nand infinite block length. Calculation of parity bits is over prior parity bits, as well as prior information bits. The memory needed to encode is about half that of comparable convolutional self-orthogonal codes. After a brief review of recent work involving two-error-correcting orchard codes [1], [2], the authors present a method of analysis of orchard codes to establish whether minimal distance criteria are met. It is assumed that parity is taken over three bits per track. The code introduced by Scott and Goetschel [1], and a truncated version of the code designed by Shiozaki [2], are then analyzed. New orchard codes, designed on the basis of the analysis method, are presented. The method is extendible to codes designed to correct more than two errors, although extension beyond three errors is computationally intensive.

Kautz, in the above paper1has presented a method of correcting single errors in SIB3codes that does not displace the count by more than two counts in the counting sequence, assuming the two most significant bits are correct. This paper presents a correction method that does not require the two most significant bits to be correct and does not displace the count by more than one in the counting sequence. Some incorrect conversion formulas in the Kautz article are corrected.

An algorithmic procedure is presented which produces an optimal two-level multiple-output network. In agreement with procedures suggested by other authors, the set of given (incompletely specified) Boolean functions of variables xi is transformed into a single (mosaic) function f( y,x) by using additional variables yi, related to the structure of the resulting network. The agreement ends here, however. It is shown that the function f(y, x) can be composed in such a way that the following statement can be proven as true.

A method is presented for determining minimal sets of distinct literals for a logically passive function, i.e. one which can be implemented, using only AND and OR gates.The first step in the procedure is the determination of vacuous variables by an examination of the truth table.The resulting table is then expanded to include one column for each variable and the complement of each variable.Columns are examined to determine which ones can be deleted and yet leave the function logically passive.The procedure for deleting columns is considered in detail, together with the effects of deleting the columns.Certain columns can be deleted on the basis of information within the column, others on the basis of a comparison of columns.These criteria are then examined in the light of (1) the effect of column removal on the ability to remove other columns, and (2) the effect of column removal on the ability to obtain at least one minimal solution.The criteria are compared with the dominance relations which are used in solving for minimal solutions from prime implicant tables.Finally, a means of detecting certain absolutely minimal forms is presented.