Rough set theory is a popular and powerful machine learning tool. It is especially suitable for dealing with information systems that exhibit inconsistencies, i.e. objects that have the same values for the conditional attributes but a different value for the decision attribute. In line with the emerging granular computing paradigm, rough set theory groups objects together based on the indiscernibility of their attribute values. Fuzzy rough set theory extends rough set theory to data with continuous attributes, and detects degrees of inconsistency in the data. Key to this is turning the indiscernibility relation into a gradual relation, acknowledging that objects can be similar to a certain extent. In very large datasets with millions of objects, computing the gradual indiscernibility relation (or in other words, the soft granules) is very demanding, both in terms of runtime and in terms of memory. It is however required for the computation of the lower and upper approximations of concepts in the fuzzy rough set analysis pipeline. Current non-distributed implementations in R are limited by memory capacity. For example, we found that a state of the art non-distributed implementation in R could not handle 30,000 rows and 10 attributes on a node with 62GB of memory. This is clearly insufficient to scale fuzzy rough set analysis to massive datasets. In this paper we present a parallel and distributed solution based on Message Passing Interface (MPI) to compute fuzzy rough approximations in very large information systems. Our results show that our parallel approach scales with problem size to information systems with millions of objects. To the best of our knowledge, no other parallel and distributed solutions have been proposed so far in the literature for this problem.

At-speed delay testing is inevitable for improving the test quality of modern high-speed semiconductor chips. This paper presents a scan cell architecture for at-speed testing of delay faults in inter-clock logic. The technique utilizes commercially available ATPG tools for test pattern generation and internal PLL clocks for test pattern application. The hardware modification is contained within the scan cells and no additional global routing is required. Simulation results using three industrial designs demonstrate that the technique is effective in detecting delay faults in inter-clock logic.

In the petrochemical industry, the product quality reflects the commercial and operational performance of a manufacturing process. However, real-time measurement of product quality is generally difficult. Online prediction of quality using readily available, frequent process measurements would be beneficial in terms of operation and quality control. In this paper, a novel soft sensor technology based on partial least squares (PLS) regression is developed and applied to a refining process for quality prediction. The modeling process is described, with emphasis on data preprocessing, multivariate-outlier detection and variables selection. Enhancement of PLS strategy is also discussed for taking into account the dynamics in the process data. The proposed approach is applied to data from a refining process and the performance of the resulting soft sensor is evaluated by comparison with laboratory data and analyzer measurements.

BACKGROUND: Clustering techniques are routinely used in gene expression data analysis to organize the massive data. Clustering techniques arrange a large number of genes or assays into a few clusters while maximizing the intra-cluster similarity and inter-cluster separation. While clustering of genes facilitates learning the functions of un-characterized genes using their association with known genes, clustering of assays reveals the disease stages and subtypes. Many clustering algorithms require the user to specify the number of clusters a priori. A wrong specification of number of clusters generally leads to either failure to detect novel clusters (disease subtypes) or unnecessary splitting of natural clusters. RESULTS: We have developed a novel method to find the number of clusters in gene expression data. Our procedure evaluates different partitions (each with different number of clusters) from the clustering algorithm and finds the partition that best describes the data. In contrast to the existing methods that evaluate the partitions independently, our procedure considers the dynamic rearrangement of cluster members when a new cluster is added. Partition quality is measured based on a new index called Net InFormation Transfer Index (NIFTI) that measures the information change when an additional cluster is introduced. Information content of a partition increases when clusters do not intersect and decreases if they are not clearly separated. A partition with the highest Total Information Content (TIC) is selected as the optimal one. We illustrate our method using four publicly available microarray datasets. CONCLUSION: In all four case studies, the proposed method correctly identified the number of clusters and performs better than other well known methods. Our method also showed invariance to the clustering techniques.

BACKGROUND: Time-course microarray experiments are being increasingly used to characterize dynamic biological processes. In these experiments, the goal is to identify genes differentially expressed in time-course data, measured between different biological conditions. These differentially expressed genes can reveal the changes in biological process due to the change in condition which is essential to understand differences in dynamics. RESULTS: In this paper, we propose a novel method for finding differentially expressed genes in time-course data and across biological conditions (say C1 and C2). We model the expression at C1 using Principal Component Analysis and represent the expression profile of each gene as a linear combination of the dominant Principal Components (PCs). Then the expression data from C2 is projected on the developed PCA model and scores are extracted. The difference between the scores is evaluated using a hypothesis test to quantify the significance of differential expression. We evaluate the proposed method to understand differences in two case studies (1) the heat shock response of wild-type and HSF1 knockout mice, and (2) cell-cycle between wild-type and Fkh1/Fkh2 knockout Yeast strains. CONCLUSION: In both cases, the proposed method identified biologically significant genes.

Boundary-scan (B-S) strategies require successful coordination of B-S activities for the devices integrated on boards and systems. The original Boundary-Scan Master (BSM) chip was developed to achieve this coordination. We have recently designed the next generation version, named BSM2, that provides a more flexible architecture and a more complete set of features as compared to the original BSM. In this paper, we describe the architectural features of BSM2 device highlighting various scan modes, automatic scan sequencing and gated clock support. We also describe the verification and testing strategies for the design including the backward compatibility with the original BSM features. DFT structures are added to the device to achieve both high fault coverage and self-test capability, as this device forms the test conduit for board and system-level testing. Finally, we briefly discuss the device support for addressable scan port (ASP) protocol and its usage in DSP applications.

Pseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones. The testing ensures detection of all detectable multiple stuck-at faults in the circuit and all detectable combinational faults within individual cones. Test pattern generators based on coding theory principles are not tailored to a specific circuit as they do not utilize any structural information. They usually generate test sets that are several orders of magnitude larger than the minimum size pseudoexhaustive test set required for a specific circuit. In this paper, we describe hardware efficient test pattern generators that employ knowledge of the circuit output cone structures for generating minimal test sets. Using our techniques, we have designed generators that generate minimum size test sets for the ISCAS benchmark circuits.

Pseudoexhaustive testing involves applying all possible input patterns to the individual output cones of a combinational circuit. Based on our new algebraic results, we have derived both generic (cone-independent) and circuit-specific (cone-dependent) bounds on the minimal length of a test required so that each cone in a circuit is exhaustively tested. For any circuit with five or fewer outputs, and where each output has k or fewer inputs, we show that the circuit can always be pseudoexhaustively tested with just 2/sup k/ patterns. We derive a tight upper bound on pseudoexhaustive test length for a given circuit by utilizing the knowledge of the structure of the circuit output cones. Since our circuit-specific bound is sensitive to the ordering of the circuit inputs, we show how the bound can be improved by permuting these inputs.

Rendering deformable volume data currently needs separate processes for deformation and rendering, and is expensive in terms of both computational and memory costs. Recognizing the importance of unifying these processes, we present a new approach to the direct rendering of deformable volumes without explicitly constructing the intermediate deformed volumes. The volume deformation is done by a radial basis function that is piecewise linearly approximated by an adaptive subdivision of the octree encoded target volume. The octree blocks in the target volume are then projected, reverse morphed and texture mapped, using the SGI 3D texture mapping hardware, in a back-to-front order. A template-based Z-plane/block intersection method is used to expedite the block projection computation.

Pseudo-exhaustive testing involves applying all possible input patterns to individual output cones of a circuit.Circuits with output cones driven

Pseudo-exhaustive testing involves applying all possible input patterns to individual output cones of a circuit. The testing ensures detection of all combinational faults within individual cones. Test pattern generators based on coding theory principles are not tailored for circuit-under-test and generate inefficient pseudo-exhaustive test sets. We shall describe novel hardware efficient test pattern generators that employ knowledge of the circuit output cone structures for generating minimal test sets. Using our techniques, we have designed generators that generate minimum test sets for partitioned versions of the combinational benchmark circuits.>

Pseudo-exhaustive testing of combinational circuits usually requires multiple test sessions and/or more than a minimum number of test signals, i.e. unique input sequences. This paper presents a methodology for partitioning combinational circuits such that they can be pseudo-exhaustively tested with a minimal number of test signals in a single test session. Circuits are logically partitioned during test mode and unrelated inputs are combined to achieve maximal test concurrency.>