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Peter H. Oden

dblp:17/4907 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1971
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 50% Parallel and multicore computing · 50%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing
partitioning and mapping		 0.011971
A Heuristic Procedure for the Partitioning and Mapping of Computer Logic Graphs · IEEE Trans. Computers 1971
Electronic design automation
physical design		 0.011971
A Heuristic Procedure for the Partitioning and Mapping of Computer Logic Graphs · IEEE Trans. Computers 1971

Methods — techniques the papers use, named apart from their topics

heuristic procedure · 0.0
YearPublicationVenuePosition
1971 A Heuristic Procedure for the Partitioning and Mapping of Computer Logic Graphs
abstract
A heuristic procedure for partitioning or mapping a set of interconnected blocks into subsets called modules is presented. Each module may be constrained in terms of the number of blocks and/or the number of intermodule connections that it can accommodate. The procedure allows given blocks to be mapped to more than one module in order to reduce the number of modules required if such reduction is desirable. Results obtained from applying the procedure, by means of a computer program, to the partitioning and mapping of computer logic gates into chips and cards are presented.
Roy L. Russo, Peter H. Oden, Peter K. Wolff Sr.
 IEEE Trans. Computers2