In cache based multiprocessors a protocol must maintain coherence among replicated copies of shared writable data. In delayed consistency protocols the effect of out-going and in-coming invalidations or updates are delayed. Delayed coherence can reduce processor blocking time as well as the effects offalse sharing. In this paper, we introduce several implementations of delayed consistency for cache-based systems in the framework of a weakly­ ordered consistency model. A performance comparison of the delayed protocols with the corre sponding On-the-Fly (non-delayed) consistency protocol is made, through execution-driven simulations of four parallel algorithms. The results show that,for parallel programs in which false sharing is a problem, significant reductions in the data miss rate of paraUel programs can be obtained with just a small incre ase in the cost and complexity of the cache system.

Simulation is used to analyze shared block contention in eight parallel algorithms and its effects on the performance of a cache coherence protocol under the assumption of infinite cache sizes. A simple program model for data and block sharing is introduced, and an analytical closed-form solution is found for all components of the cache coherence overhead. This model is based on the observation that shared writable blocks are accessed in critical or in semicritical sections. The program model is applied to the analysis of multiprocessor systems with finite cache sizes and for steady state computations. The authors compare the model predictions to the results of execution-driven simulations of eight parallel algorithms. The simulation is conducted for various numbers of processors and different cache block sizes.>