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Kazumitsu Takeda

dblp:17/6765 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1989
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
High-performance computing · 44% Parallel and multicore computing · 22% Processor architecture and microarchitecture · 22%

Topics — the 5 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › computer arithmetic
extended precision
0.011989
R256: A Research Parallel Processor for Scientific Computation · ISCA 1989
High-performance computing › numerical computation
floating point computation
0.011989
R256: A Research Parallel Processor for Scientific Computation · ISCA 1989
Parallel and multicore computing › parallel architecture
parallel processor
0.011989
R256: A Research Parallel Processor for Scientific Computation · ISCA 1989
Performance modeling and evaluation › simulation
monte carlo simulation
0.011989
R256: A Research Parallel Processor for Scientific Computation · ISCA 1989
Electronic design automation › technology computer-aided design
semiconductor device simulation
0.011989
R256: A Research Parallel Processor for Scientific Computation · ISCA 1989

Methods — techniques the papers use, named apart from their topics

distributed parallel network design · 0.0VLSI processor design · 0.0
YearPublicationVenuePosition
1989 R256: A Research Parallel Processor for Scientific Computation
abstract
A scientific parallel processor called the R256 has been developed. The R256 is composed of 16x16 processing elements, and has the outstanding features of a “distributed parallel network” as well as on IEEE 80-bit extended floating point computation ability. The computation accuracy, required by an exhaustive number of iterations in scientific computations, is resolved by the dedicated 80-bit VLSI processor, which was developed here for the R256. The innovative distributed parallel network was designed so as to effectively resolve heavy communication problems, which are found in applications based on the Monte Carlo simulation technique. The R256 network was very economical at a hardware cost of √N-folds (16 folds in this case) to that of an ideal full-crossbar switch, at the same time keeping the rates comparable to that of an ideal switch. The R256 demonstrates high performance of 2-GB/s data transfer rates and 500-MFLOPS computation rates on a semiconductor device simulation application.
Tomoo Fukazawa, Takashi Kimura, Masaaki Tomizawa, Kazumitsu Takeda, Yoshitaka Itoh
ISCA4