Designing analog circuits from performance specifications is a complex, multi-stage process encompassing topology selection, parameter inference, and layout feasibility. We introduce FALCON, a unified machine learning framework that enables fully automated, specification-driven analog circuit synthesis through topology selection and layout-constrained optimization. Given a target performance, FALCON first selects an appropriate circuit topology using a performance-driven classifier guided by human design heuristics. Next, it employs a custom, edge-centric graph neural network trained to map circuit topology and parameters to performance, enabling gradient-based parameter inference through the learned forward model. This inference is guided by a differentiable layout cost, derived from analytical equations capturing parasitic and frequency-dependent effects, and constrained by design rules. We train and evaluate FALCON on a large-scale custom dataset of 1M analog mm-wave circuits, generated and simulated using Cadence Spectre across 20 expert-designed topologies. Through this evaluation, FALCON demonstrates >99\% accuracy in topology inference, <10\% relative error in performance prediction, and efficient layout-aware design that completes in under 1 second per instance. Together, these results position FALCON as a practical and extensible foundation model for end-to-end analog circuit design automation.

We present a mm-wave low-phase-noise (PN) and power-efficient super-harmonic voltage controlled oscillator (VCO) based on a new PN and harmonic power manipulation technique by shaping voltage waveforms. By observing the effect of relative amplitude and phase of fundamental and second harmonic voltage components across the transistor terminals, it is shown how the impulse sensitivity function (ISF) associated with the noise of transistor as well as generated harmonic power by the active device are inter-related. By systematically choosing the passive embedding of the transistor inside the proposed VCO, it is shown how the circuit can achieve a very low PN while maintaining a high harmonic power generation efficiency. The proposed VCO is fabricated in 65-nm Bulk CMOS technology and achieves a measured frequency tuning range (FTR) of 76–82 GHz with a PN of -109.8 dBc/Hz at 1MHz offset frequency, and a peak figure-of-merit (FoM) of 189.3 dBc/Hz. The proposed VCO demonstrates a 4.6% DC-to-RF efficiency and a peak output power of -0.6 dBm. To the best of our knowledge, This work demonstrates the highest FOM among Si/SiGe varactor-based oscillators operating at this frequency band, to date.

Automated design of analog and radio-frequency circuits using supervised or reinforcement learning from simulation data has recently been studied as an alternative to manual expert design. It is straightforward for a design agent to learn an inverse function from desired performance metrics to circuit parameters. However, it is more common for a user to have threshold performance criteria rather than an exact target vector of feasible performance measures. In this work, we propose a method for generating from simulation data a dataset on which a system can be trained via supervised learning to design circuits to meet threshold specifications. We moreover perform the to-date most extensive evaluation of automated analog circuit design, including experimenting in a significantly more diverse set of circuits than in prior work, covering linear, nonlinear, and autonomous circuit configurations, and show that our method consistently reaches success rate better than 90% at 5% error margin, while also improving data efficiency by upward of an order of magnitude.

Analog to Digital Converters (ADCs) are a major contributor to the energy consumption on the receiver side of millimeter-wave multiple-input multiple-output (MIMO) systems with large antenna arrays. Consequently, there has been significant interest in using low-resolution ADCs along with hybrid beamforming at MIMO receivers for energy efficiency. However, decreasing the ADC resolution results in performance loss — in terms of achievable rates — due to increased quantization error. In this work, we study the application of practically implementable nonlinear analog operations, prior to sampling and quantization at the ADCs, as a way to mitigate the afore-mentioned rate-loss. A receiver architecture consisting of linear analog combiners, implementable nonlinear analog operators, and one-bit threshold ADCs is designed. The fundamental information theoretic performance limits of the resulting communication system, in terms of achievable rates, are investigated under various assumptions on the set of implementable nonlinear analog functions. In order to justify the feasibility of the nonlinear operations in the proposed receiver architecture, an analog circuit is introduced, and circuit simulations exhibiting the generation of the desired nonlinear analog operations are provided.