This paper presents a parameterized soft core generator for the discrete Fourier transform (DFT). Reusable IPs of digital signal processing (DSP) kernels are important time-saving resources in DSP hardware development. Unfortunately, reusable IPs, however optimized, can introduce inefficiencies because they cannot fit the exact requirements of every application context. Given the well-understood and regular computation in DSP kernels, an automatic tool can generate high-quality ready-to-use IPs customized to user-specified cost/performance tradeoffs (beyond basic parameters such as input size and data format). The paper shows that the generated DFT cores can match closely the performance and cost of DFT cores from the Xilinx LogiCore library. Furthermore, the generator can yield DFT cores over a range of different performance/ cost tradeoff points that are not available from the library.

The abstract transition system (ATS) is a high-level hardware description framework. ATS's operation-centric abstraction permits perspicuous descriptions of complex concurrent hardware behavior as a sequence of atomic state transitions. However non-determinism in the ATS semantics prevents it from capturing the behavior of systems whose correctness depends upon both function and exact synchronous timing. To address this shortcoming, we present two extensions to ATS-committing transitions and synchronously delayed expressions-to support the specification of synchronous behaviors and interfaces. The new synchronous extensions compose naturally with the original ATS. We describe a compilation strategy for the synchronous extensions that leverages existing ATS synthesis capabilities. We also evaluate the new extensions' ease of description and synthesis quality in several design examples.